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1.发明授权Self-aligned carbon nanostructure field effect transistors using selective dielectric deposition 有权使用选择性电介质沉积的自对准碳纳米结构场效应晶体管公开(公告)号：US08785262B2
公开(公告)日：2014-07-22
申请号：US13610991
申请日：2012-09-12
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78669 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/775 , H01L29/78678 , H01L29/78696 , H01L51/0048 , H01L51/0516 , Y10S977/742
摘要： Self-aligned carbon nanostructure field effect transistor structures are provided, which are foamed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.
摘要翻译： 提供了自对准碳纳米结构场效应晶体管结构，其使用选择性电介质沉积技术发泡。 例如，晶体管器件包括绝缘衬底和嵌入绝缘衬底中的栅电极。 在围绕栅电极的绝缘基板的表面上形成介电沉积禁止层。 选择性地在栅电极上形成栅极电介质。 沟道结构（例如碳纳米结构）设置在栅极电介质上钝化层选择性地形成在栅极电介质上。 源极和漏极触点形成在与沟道结构接触的钝化层的相对侧上。 当选择性地形成栅极电介质和钝化层时，介电沉积禁止层防止介电材料沉积在围绕栅电极的绝缘层的表面上。
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公开(公告)号：US08680512B2
公开(公告)日：2014-03-25
申请号：US13614530
申请日：2012-09-13
申请人： Phaedon Avouris , Damon B. Farmer , Yu-Ming Lin , Yu Zhu
发明人： Phaedon Avouris , Damon B. Farmer , Yu-Ming Lin , Yu Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/1606 , H01L29/41733 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/778 , H01L29/78684
摘要： A transistor structure is provided which includes a graphene layer located on an insulating layer, a first metal portion overlying a portion of the graphene layer, a second metal portion contacting and overhanging the first metal portion, a first electrode contacting a portion of the graphene layer and laterally offset from a first sidewall of the first metal portion by a lateral spacing, and a second electrode contacting another portion of the graphene layer and laterally offset from a second sidewall of the first metal portion by the lateral spacing.
摘要翻译： 提供一种晶体管结构，其包括位于绝缘层上的石墨烯层，覆盖石墨烯层的一部分的第一金属部分，与第一金属部分接触并悬垂的第二金属部分，与石墨烯层的一部分接触的第一电极 并且横向间隔地从第一金属部分的第一侧壁偏移，并且第二电极接触石墨烯层的另一部分，并且横向间隔地与第一金属部分的第二侧壁横向偏移。
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3.发明授权Bilayer gate dielectric with low equivalent oxide thickness for graphene devices 失效双层栅极电介质，石墨烯器件的等效氧化物厚度低公开(公告)号：US08680511B2
公开(公告)日：2014-03-25
申请号：US13369901
申请日：2012-02-09
申请人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Yu-Ming Lin , Deborah A. Neumayer , Dirk Pfeiffer , Wenjuan Zhu
发明人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Yu-Ming Lin , Deborah A. Neumayer , Dirk Pfeiffer , Wenjuan Zhu
IPC分类号： H01L29/06
CPC分类号： H01L21/0237 , B82Y30/00 , B82Y40/00 , H01L21/02378 , H01L21/02527 , H01L21/02617 , H01L21/02661 , H01L29/1606 , H01L29/4908 , H01L29/513 , H01L29/66045 , H01L29/7781 , H01L29/78684
摘要： A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.
摘要翻译： 在石墨烯层的最上表面上设置氮化硅层，然后在氮化硅层的最上表面上设置二氧化铪层。 氮化硅层用作二氧化铪层的润湿剂，从而防止在石墨烯层顶上形成不连续的二氧化铪塔。 共同形成低EOT双层栅极电介质的氮化硅层和二氧化铪层在石墨烯层的顶部呈现连续的形态。
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4.发明申请DOPING OF SEMICONDUCTOR SUBSTRATE THROUGH CARBONLESS PHOSPHOROUS-CONTAINING LAYER 有权通过无碳磷酸盐层对二氧化硅基底进行掺杂公开(公告)号：US20110223751A1
公开(公告)日：2011-09-15
申请号：US12721727
申请日：2010-03-11
IPC分类号： H01L21/225 , B05C3/02
CPC分类号： H01L21/225 , H01L21/2254
摘要： A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.
摘要翻译： 公开了用于掺杂半导体衬底的方法和系统。 在一个实施方案中，该方法包括在半导体衬底上形成无磷的磷酸层，并且从磷酸层中扩散磷在衬底中以在其中形成活化的磷掺杂剂。 在一个实施例中，将半导体衬底浸入磷化合物的溶液中以在衬底上形成磷化合物层，并且将该层磷加工形成磷酸层。 在一个实施方案中，该处理可以包括水解磷化合物的层以形成磷酸层。 在一个实施例中，在磷酸层上形成氧化物覆盖层以形成封盖的基底。 封装的衬底可以退火以在衬底中扩散磷并形成活化的掺杂剂。
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5.发明申请公开(公告)号：US20110101308A1
公开(公告)日：2011-05-05
申请号：US12611421
申请日：2009-11-03
申请人： Phaedon Avouris , Damon B. Farmer , Fengnian Xia
发明人： Phaedon Avouris , Damon B. Farmer , Fengnian Xia
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/4908 , H01L29/66742 , H01L29/78606 , H01L29/78684
摘要： A fabrication process for a nanoelectronic device and a device are provided. Channel material is deposited on a substrate to form a channel. A source metal contact and a drain metal contact are deposited on the channel material, and the source metal contact and the drain metal contact are on opposing ends of the channel material. A polyhydroxystyrene derivative is deposited on the channel material. A top gate oxide is deposited on the polymer layer. A top gate metal is deposited on the top gate oxide.
摘要翻译： 提供了一种用于纳米电子器件和器件的制造工艺。 通道材料沉积在基底上以形成通道。 源极金属触点和漏极金属触点沉积在沟道材料上，源极金属触点和漏极金属触点位于沟道材料的相对端上。 多羟基苯乙烯衍生物沉积在通道材料上。 顶栅氧化物沉积在聚合物层上。 顶栅极金属沉积在顶栅氧化物上。
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公开(公告)号：US09425406B2
公开(公告)日：2016-08-23
申请号：US13344738
申请日：2012-01-06
申请人： Roy G. Gordon , Damon B. Farmer
发明人： Roy G. Gordon , Damon B. Farmer
IPC分类号： C23C16/00 , H01B1/00 , H01L51/00 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B31/02 , C01F7/30 , H01L51/05
CPC分类号： H01L51/0049 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/174 , C01B2202/02 , C01F7/304 , C01P2004/13 , H01L51/057 , H01L51/0595 , Y10S977/734 , Y10S977/755 , Y10S977/842 , Y10S977/847 , Y10S977/89 , Y10T428/2918
摘要： There are provided methods for functionalizing a planar surface of a microelectronic structure, by exposing the surface to at least one vapor including at least one functionalization species, such as NO2 or CH3ONO, that non-covalently bonds to the surface while providing a functionalization layer of chemically functional groups, to produce a functionalized surface. The functionalized surface is exposed to at least one vapor stabilization species that reacts with the functionalization layer to form a stabilization layer that stabilizes the functionalization layer against desorption from the planar microelectronic surface while providing chemically functional groups. The stabilized surface is exposed to at least one material layer precursor species that deposits a material layer on the stabilized planar microelectronic surface. The stabilized planar microelectronic surface can be annealed at a peak annealing temperature that is less than about 700° C.
摘要翻译： 提供了通过将表面暴露于至少一种包含非共价结合表面的官能化物质（例如NO 2或CH 3 ONO）的蒸气的表面而提供微电子结构的平坦表面的方法，同时提供 化学官能团，以产生官能化表面。 功能化表面暴露于与官能化层反应的至少一种汽相稳定物质，以形成稳定层，该稳定层使官能化层抵抗来自平面微电子表面的解吸，同时提供化学官能团。 稳定的表面暴露于在稳定的平面微电子表面上沉积材料层的至少一种材料层前体物质。 稳定的平面微电子表面可以在小于约700℃的峰值退火温度下退火
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公开(公告)号：US08803130B2
公开(公告)日：2014-08-12
申请号：US13492097
申请日：2012-06-08
申请人： Ali Afzali-Ardakani , Phaedon Avouris , Damon B. Farmer , Yu-Ming Lin , Yu Zhu
发明人： Ali Afzali-Ardakani , Phaedon Avouris , Damon B. Farmer , Yu-Ming Lin , Yu Zhu
IPC分类号： H01L29/06
CPC分类号： H01L29/1606 , H01L29/42376 , H01L29/66431 , H01L29/7781 , Y10S977/734
摘要： Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface.
摘要翻译： 公开了石墨烯晶体管器件及其制造方法。 一种这样的石墨烯晶体管器件包括源电极和漏电极以及包括设置在源极和漏极之间的电介质侧壁间隔物的栅极结构。 该器件还包括与源极和漏极电极中的至少一个相邻的石墨烯层，其中源/漏电极和石墨烯层之间的界面在整个界面处保持一致的电导率。
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8.发明授权Self-aligned carbon nanostructure field effect transistors using selective dielectric deposition 有权使用选择性电介质沉积的自对准碳纳米结构场效应晶体管公开(公告)号：US08786018B2
公开(公告)日：2014-07-22
申请号：US13610158
申请日：2012-09-11
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78669 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/775 , H01L29/78678 , H01L29/78696 , H01L51/0048 , H01L51/0516 , Y10S977/742
摘要： Self-aligned carbon nanostructure field effect transistor structures are provided, which are formed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.
摘要翻译： 提供了使用选择性电介质沉积技术形成的自对准碳纳米结构场效应晶体管结构。 例如，晶体管器件包括绝缘衬底和嵌入绝缘衬底中的栅电极。 在围绕栅电极的绝缘基板的表面上形成介电沉积禁止层。 选择性地在栅电极上形成栅极电介质。 沟道结构（例如碳纳米结构）设置在栅极电介质上钝化层选择性地形成在栅极电介质上。 源极和漏极触点形成在与沟道结构接触的钝化层的相对侧上。 当选择性地形成栅极电介质和钝化层时，介电沉积禁止层防止介电材料沉积在围绕栅电极的绝缘层的表面上。
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公开(公告)号：US08691675B2
公开(公告)日：2014-04-08
申请号：US12625835
申请日：2009-11-25
IPC分类号： H01L21/04
CPC分类号： H01L21/2254
摘要： A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.
摘要翻译： 用掺杂剂原子掺杂硅层的方法通常包括使掺杂剂前体的蒸气与存在于硅层上的氧化物和/或氢氧化物反应性位点反应以形成掺杂剂前体的自组装单层; 用水蒸汽水解掺杂剂前体的自组装单层以在掺杂剂前体上形成侧基羟基; 用氧化物层封闭自组装单层; 以及在有效地将掺杂剂原子从掺杂剂前体扩散到硅层中的温度下退火硅层。 可以以类似的方式形成另外的单层，由此提供受控的掺杂剂前体化合物的逐层气相沉积用于硅的受控掺杂。
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10.发明申请SELF-ALIGNED CARBON NANOSTRUCTURE FIELD EFFECT TRANSISTORS USING SELECTIVE DIELECTRIC DEPOSITION 有权使用选择性电介质沉积的自对准碳纳米管结构场效应晶体管公开(公告)号：US20140073093A1
公开(公告)日：2014-03-13
申请号：US13610991
申请日：2012-09-12
IPC分类号： H01L21/336
CPC分类号： H01L29/78669 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/775 , H01L29/78678 , H01L29/78696 , H01L51/0048 , H01L51/0516 , Y10S977/742
摘要： Self-aligned carbon nanostructure field effect transistor structures are provided, which are foamed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.
摘要翻译： 提供了自对准碳纳米结构场效应晶体管结构，其使用选择性电介质沉积技术发泡。 例如，晶体管器件包括绝缘衬底和嵌入绝缘衬底中的栅电极。 在围绕栅电极的绝缘基板的表面上形成介电沉积禁止层。 选择性地在栅电极上形成栅极电介质。 沟道结构（例如碳纳米结构）设置在栅极电介质上钝化层选择性地形成在栅极电介质上。 源极和漏极触点形成在与沟道结构接触的钝化层的相对侧上。 当选择性地形成栅极电介质和钝化层时，介电沉积禁止层防止介电材料沉积在围绕栅电极的绝缘层的表面上。
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