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公开(公告)号：US07924633B2
公开(公告)日：2011-04-12
申请号：US12389420
申请日：2009-02-20
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C8/08
摘要： A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.
摘要翻译： 一种用于在存储器中实现升压的字线电压的方法和字线电压升压电路，以及设置有该电路所在的设计结构。 字线升压电路接收预充电信号，使用耦合到自举电容器的开关晶体管，并响应于预充电信号产生升压电压电平。 提升的电压电平被施加到字线驱动器的输出级的电压源，导致所选字线的字线电压电平升高。 开关晶体管由预充电信号控制，并且提供升压电压电平的自举电容的节点由开关晶体管驱动为高电平。
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2.发明授权Low power level shifting latch circuits with gated feedback for high speed integrated circuits 失效低功率电平移位锁存电路，具有门控反馈用于高速集成电路公开(公告)号：US07737757B2
公开(公告)日：2010-06-15
申请号：US12178071
申请日：2008-07-23
IPC分类号： H03K19/0175
CPC分类号： H03K3/356121
摘要： Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.
摘要翻译： 具有用于高速集成电路的门控反馈的低功率电平移位器锁存电路，以及设有主题电路所在的设计结构。 操作在第一电压源的域中的锁存器输入级接收响应于通过预定时钟信号使能的数据输入。 耦合到锁存器输入级的锁存器存储元件包括在第二电压源的区域中操作的锁存器输出级提供具有与第二电压源相对应的电压电平的数据输出。 闩锁存储元件包括电平移位装置，其提供从第一电源电平到第二电压供应电平的电平移位。 锁存器存储元件包括反馈栅极器件，当数据被写入锁存器输入级时，反馈栅极器件接收预定义的时钟信号以对门锁反馈到锁存器输入级。
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3.发明申请Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability and Enhanced Area Usage 失效实现具有增强的SRAM单元稳定性和增强区域使用的Domino读取SRAM的本地评估公开(公告)号：US20100046278A1
公开(公告)日：2010-02-25
申请号：US12195151
申请日：2008-08-20
CPC分类号： G11C11/413
摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.
摘要翻译： 一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。 实现相关SRAM单元组的读和写操作的SRAM本地评估电路包括真和补补位线，真和补写写数据传播输入，预充电信号和预充电写信号。 相应的预充电装置连接在电压源VDD与真位线和补码位线之间。 第一传递门装置连接在补码位线和真实写入数据传播输入端之间。 第二个通路装置连接在真位线和补码写入数据传播输入之间。 在读取操作期间，预充电写信号禁用通路器件。 在写入操作期间，预充电写入信号使能通路装置。
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公开(公告)号：US20090323445A1
公开(公告)日：2009-12-31
申请号：US12146777
申请日：2008-06-26
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C11/41 , G11C29/1201
摘要： A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode.
摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构和用于BIST（内置自检）的高性能SRAM（静态随机存取存储器）读取旁路的集成电路。 该设计结构和集成结构包括用于SRAM阵列的读取输出的动态到静态转换单元和集成到动态到静态转换单元中的测试旁路单元，以便允许SRAM阵列的读取输出通过 在不影响性能的非测试模式下，并绕过SRAM阵列的读取输出，并允许测试信号在测试模式下通过。
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公开(公告)号：US07505340B1
公开(公告)日：2009-03-17
申请号：US11845866
申请日：2007-08-28
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A method implements static random access memory (SRAM) cell write performance evaluation. A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： 一种方法实现了静态随机存取存储器（SRAM）单元写入性能评估。 SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。 环形振荡器电路用于产生字线脉冲。 状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。 控制信号被施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元被写入。 然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。 从这些写入操作中，识别要写入单元的所需字线脉冲宽度。
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6.发明申请Method and Apparatus for Implementing SRAM Cell Write Performance Evaluation 失效实现SRAM单元写入性能评估的方法和装置公开(公告)号：US20090063912A1
公开(公告)日：2009-03-05
申请号：US11873173
申请日：2007-10-16
IPC分类号： G11C29/08
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation, and a design structure on which the subject circuit resides are provided. ASRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： 一种用于实现静态随机存取存储器（SRAM）单元写入性能评估的方法和装置，以及设置有主题电路所在的设计结构。 ASRAM内核包括只连接到一个位列的每个字线。 环形振荡器电路用于产生字线脉冲。 状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。 将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。 然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。 从这些写入操作中，识别要写入单元的所需字线脉冲宽度。
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7.发明申请METHOD AND APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION 失效用于实现SRAM单元写性能评估的方法和装置公开(公告)号：US20090059697A1
公开(公告)日：2009-03-05
申请号：US11845866
申请日：2007-08-28
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。 环形振荡器电路用于产生字线脉冲。 状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。 控制信号被施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元被写入。 然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。 从这些写入操作中，识别要写入单元的所需字线脉冲宽度。
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8.发明申请ENHANCED SRAM REDUNDANCY CIRCUIT FOR REDUCING WIRING AND REQUIRED NUMBER OF REDUNDANT ELEMENTS 审中-公开增强SRAM冗余电路，用于减少接线和需要的冗余元件数量公开(公告)号：US20080273406A1
公开(公告)日：2008-11-06
申请号：US12172318
申请日：2008-07-14
CPC分类号： G11C29/846
摘要： A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.
摘要翻译： 一种方法和增强的静态随机存取存储器（SRAM）冗余电路减少了布线和所需数量的冗余元件。 位线冗余机制允许对一对位列进行交换。 两个相邻的位线一次被换出，一个偶数和一个奇数。 交换是通过围绕不良列操作数据进行转换，并在需要时引导的末尾添加冗余列。
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公开(公告)号：US07443744B2
公开(公告)日：2008-10-28
申请号：US11559431
申请日：2006-11-14
IPC分类号： G11C7/00
CPC分类号： G11C29/846
摘要： A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.
摘要翻译： 一种方法和增强的静态随机存取存储器（SRAM）冗余电路减少了布线和所需数量的冗余元件。 位线冗余机制允许对一对位列进行交换。 两个相邻的位线一次被换出，一个偶数和一个奇数。 交换是通过围绕不良列操作数据进行转换，并在需要时引导的末尾添加冗余列。
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10.发明授权Data security for dynamic random access memory using body bias to clear data at power-up 有权使用身体偏倚的动态随机存取存储器的数据安全性，以在上电时清除数据公开(公告)号：US08467230B2
公开(公告)日：2013-06-18
申请号：US12898924
申请日：2010-10-06
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
IPC分类号： G11C11/24
CPC分类号： G11C7/24 , G11C5/145 , G11C7/20 , G11C11/4072 , G11C11/4078
摘要： A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.
摘要翻译： 电路和方法在上电时擦除存储在DRAM芯片中的所有数据，以提高数据安全性。 通过增加单元的体电压同时接通DRAM存储单元的晶体管，可以擦除所有的DRAM存储单元。 在示例电路中，通过由对存储器单元的p阱施加电压的上电复位（POR）信号控制的电荷泵增加体电压。 向p阱施加的电压降低了电池的阈值电压，使得存储器单元的NFET晶体管将导通。 当所有设备都打开时，存储在存储单元中的数据将被擦除，因为连接到通用位线的所有单元的电压合并为单个值。
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