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    System and method for correcting programming failures in a programmable fuse array
    2.
    发明授权
    System and method for correcting programming failures in a programmable fuse array 有权
    用于校正可编程保险丝阵列中的编程故障的系统和方法

    公开(公告)号：US08363502B2

    公开(公告)日：2013-01-29

    申请号：US12950780

    申请日：2010-11-19

    申请人： Daniel Rey-Losada

    发明人： Daniel Rey-Losada

    IPC分类号： G11C17/18

    CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C17/18

    摘要： A system for correcting programming failures in an M-bit primary array of programmable fuses. The address of the failed fuse is stored in a secondary fuse array. Correction logic coupled to the primary and secondary arrays propagates the programming states of the good fuses, and corrects the programming state of the failed fuse, if any. The correction logic preferably comprises a decoder coupled to the secondary array which produces a one-hot M-bit word representing the failed fuse, and combinatorial logic arranged to receive the programming states of the primary array fuses and the one-hot M-bit word at respective inputs and to produce the correction logic output. Multiple failures can be accommodated using multiple secondary arrays, each storing the address of a respective failed fuse, or a tertiary array which stores the address of a failed fuse in either the primary or secondary arrays.

    摘要翻译： 一种用于校正可编程保险丝的M位初级阵列中的编程故障的系统。 故障保险丝的地址存储在次级保险丝阵列中。 耦合到主和次级阵列的校正逻辑传播良好保险丝的编程状态，并校正失效保险丝的编程状态（如果有的话）。 校正逻辑优选地包括耦合到次级阵列的解码器，其产生表示故障保险丝的单热M位字，以及组合逻辑，被布置为接收主阵列熔丝和单热M位字的编程状态 并产生校正逻辑输出。 可以使用多个次级阵列来容纳多个故障，每个副阵列存储相应的故障保险丝的地址，或在主阵列或副阵列中存储故障保险丝的地址的第三阵列。