公开(公告)号：US4783733A

公开(公告)日：1988-11-08

申请号：US853927

申请日：1986-04-21

申请人： David A. Greig ,  David L. Hinders ,  William R. Goodman

发明人： David A. Greig ,  David L. Hinders ,  William R. Goodman

IPC分类号： G06F11/16 ,  G06F13/38 ,  G06F15/20

CPC分类号： G06F13/385 ,  G06F11/16

摘要： The present invention relates to a system for controlling multiple communications lines, so that a computer system can operate with a single component failure. Two processors are used to control two communications controllers and each of the controllers control up to 15 line controllers. Each line controller has two ports and each port is connected to a communications controller thereby providing two communications paths to each processor. Two power supplies are also used to provide single failure fault-tolerance. A downloadable microprocessor is provided in combination with, but separate from, an interface board that is designed to meet various communication format specifications and the line controller comprises the two boards.

摘要翻译： 本发明涉及一种用于控制多条通信线路的系统，使得计算机系统可以以单个部件故障进行操作。 两个处理器用于控制两个通信控制器，每个控制器控制多达15个线路控制器。 每个线路控制器具有两个端口，并且每个端口连接到通信控制器，从而为每个处理器提供两条通信路径。 两个电源也用于提供单一故障容错。 可下载的微处理器与设计用于满足各种通信格式规范的接口板组合但是分开地提供，并且线路控制器包括两个板。

公开(公告)号：US4817091A

公开(公告)日：1989-03-28

申请号：US52094

申请日：1987-05-19

申请人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

发明人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

IPC分类号： G06F11/18 ,  G06F1/26 ,  G06F5/06 ,  G06F7/78 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/28 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173

CPC分类号： G06F7/78 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/2007 ,  G06F11/2015 ,  G06F11/2023 ,  G06F11/2035 ,  G06F11/2043 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/14 ,  G06F12/1458 ,  G06F13/122 ,  G06F13/20 ,  G06F13/287 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F5/06

摘要： In a multiprocessor system interconnected by a bus structure that provides communication and information transfers between the processor modules of the system, each processor broadcasts a central message to all the other processors of the system on a periodic basis. A processor module not receiving the control message from a sending processor module will assume the sending processor module has failed, and operate to take over the task of the failed processor module.

摘要翻译： 在通过提供系统的处理器模块之间的通信和信息传输的总线结构互连的多处理器系统中，每个处理器周期性地向系统的所有其他处理器广播中央消息。 没有从发送处理器模块接收控制消息的处理器模块将假定发送处理器模块已经失败，并且操作以接管故障处理器模块的任务。

公开(公告)号：US4807116A

公开(公告)日：1989-02-21

申请号：US52095

申请日：1987-05-18

申请人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

发明人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

IPC分类号： G06F11/18 ,  G06F1/26 ,  G06F5/06 ,  G06F7/78 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/28 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F13/36 ,  G06F13/42

CPC分类号： G06F7/78 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/2007 ,  G06F11/2015 ,  G06F11/2023 ,  G06F11/2035 ,  G06F11/2043 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/14 ,  G06F12/1458 ,  G06F13/122 ,  G06F13/20 ,  G06F13/287 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F5/06

摘要： In a multiprocessor system comprising a plurality of individual processor modules interconnected by a bus structure, including a bus controller, for providing communication between the processor modules, a method and apparatus for interprocessor communication includes one of the processor modules sending a request signal to the bus controller to request a transmission; the bus controller polling the processor modules to identify the requesting processor module; the requestor processor module responding to the poll with the identification of the receiver processor module; the bus controller interrogating the receiver processor module to determine its status (i.e., busy or available); and the bus controller then signaling transmission commencement.

摘要翻译： 在包括由包括总线控制器在内的总线控制器互连的多个单独处理器模块的多处理器系统中，用于提供处理器模块之间的通信，用于处理器间通信的方法和装置包括处理器模块之一向总线发送请求信号 控制器请求传输; 总线控制器轮询处理器模块以识别请求处理器模块; 所述请求者处理器模块用所述接收器处理器模块的标识响应所述轮询; 总线控制器询问接收机处理器模块以确定其状态（即忙或可用）; 并且总线控制器然后信令传输开始。

公开(公告)号：US4607365A

公开(公告)日：1986-08-19

申请号：US551283

申请日：1983-11-14

申请人： David A. Greig ,  David L. Hinders ,  William R. Goodman

发明人： David A. Greig ,  David L. Hinders ,  William R. Goodman

IPC分类号： H04L29/14 ,  G06F3/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F13/38 ,  G06F15/16

CPC分类号： G06F11/2007 ,  G06F11/16 ,  G06F11/2005 ,  G06F13/385 ,  G06F11/14 ,  G06F11/22

摘要： The present invention relates to a system for controlling multiple communications lines, so that a computer system can operate with a single component failure. Two processors are used to control two communications controllers and each of the controllers control up to 15 line controllers. Each line controller has two ports and each port is connected to a communications controller thereby providing two communications paths to each processor. Redundant power supplies are also used to provide single failure fault-tolerance. A downloadable microprocessor board is provided in combination with, but separate from, an interface board that is designed to meet various communication format specifications and the line controller comprises the two boards.

摘要翻译： 本发明涉及一种用于控制多条通信线路的系统，使得计算机系统可以以单个部件故障进行操作。 两个处理器用于控制两个通信控制器，每个控制器控制多达15个线路控制器。 每个线路控制器具有两个端口，并且每个端口连接到通信控制器，从而为每个处理器提供两条通信路径。 两个电源也用于提供单一故障容错。 此外，本公开涉及提供一种与被设计为满足各种通信格式规范的接口板组合但分开的可下载微处理器板，并且线路控制器包括两个板。 使用单个微处理器板可提高生产率，可维护性和诊断能力。

公开(公告)号：US4378588A

公开(公告)日：1983-03-29

申请号：US147091

申请日：1980-05-06

申请人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

发明人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

IPC分类号： G06F11/18 ,  G06F1/26 ,  G06F5/06 ,  G06F7/78 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/28 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G11C9/00

CPC分类号： G06F7/78 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/2007 ,  G06F11/2015 ,  G06F11/2023 ,  G06F11/2035 ,  G06F11/2043 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/14 ,  G06F12/1458 ,  G06F13/122 ,  G06F13/20 ,  G06F13/287 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F5/06

摘要： A datapath system and protocol is disclosed in which data is transferred between a computer memory and one or more peripheral devices through device controllers, each of which includes a buffer, through periodic connection of the device controller to the channel. The system and protocol are structured to permit multiple device controllers to cooperatively interact on a single channel, without direct communication between device controllers. Each device controller monitors the level of stress on its buffer and at appropriate times presents a reconnect request to the channel, together with indica for permitting the channel to determine the priority of a particular request relative to other reconnect requests. The times at which a reconnect signal should be presented are determined by monitoring the level of information storage in the buffer and relating that level to a threshold level; both overfilling and overemptying are prevented. The threshold level can be varied in accordance with a criteria which makes allowance for the number and combination of device controllers attached to the channel; and is set such that the remaining space in the buffer is sufficient to allow the buffer to transfer data to or from the associated peripheral device, at the rate demanded by that peripheral device, long enough to allow the channel to connect to one lower priority device controller, and all higher priority device controllers. The threshold level and buffer size are also set such that, after a reconnect, the buffer is capable of transferring data to or from the associated peripheral device, at the rate demanded by the peripheral, long enough for the channel to reconnect to all lower priority device controllers, to ensure that all device controllers, no matter the priority, are allowed access to the channel. The invention has broad application, but is particularly well-suited to fault tolerant computing systems.

摘要翻译： 公开了一种数据路径系统和协议，其中数据通过设备控制器在计算机存储器和一个或多个外围设备之间传送，每个设备控制器通过设备控制器到通道的周期性连接而包括缓冲器。 系统和协议被构造成允许多个设备控制器在单个信道上协作地交互，而不需要设备控制器之间的直接通信。 每个设备控制器监视其缓冲器上的压力水平，并且在适当的时间向通道呈现重新连接请求，以及用于允许信道确定特定请求相对于其他重新连接请求的优先级的标记。 通过监视缓冲器中的信息存储的级别并将该级别与阈值级别相关联来确定应该呈现重新连接信号的时间; 防止过度填充和过度捕捞。 可以根据允许附加到信道的设备控制器的数量和组合的标准来改变阈值水平; 并且被设置为使得缓冲器中的剩余空间足以允许缓冲器按照该外围设备所要求的速率将数据传送到相关联的外围设备或从相关联的外围设备传输数据，其长度足以允许信道连接到一个较低优先级的设备 控制器和所有较高优先级的设备控制器。 阈值电平和缓冲器大小也被设置为使得在重新连接之后，缓冲器能够以相应的外围设备的数据传输数据，以外围设备要求的速率足以使信道重新连接到所有较低优先级 设备控制器，以确保所有设备控制器，无论优先级，都允许访问该通道。 本发明具有广泛的应用，但是特别适用于容错计算系统。

公开(公告)号：US4672537A

公开(公告)日：1987-06-09

申请号：US727614

申请日：1985-04-29

申请人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

发明人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

IPC分类号： G06F11/18 ,  G06F1/26 ,  G06F5/06 ,  G06F7/78 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/28 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173

CPC分类号： G06F7/78 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/2007 ,  G06F11/2015 ,  G06F11/2023 ,  G06F11/2035 ,  G06F11/2043 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/14 ,  G06F12/1458 ,  G06F13/122 ,  G06F13/20 ,  G06F13/287 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F5/06

摘要： A multiprocessor system of the kind in which two or more separate processor modules are interconnected for parallel processing includes interprocessor buses dedicated exclusively to interprocessor communication. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. An enable latch in each port dynamically disables that port from placing any signals on the related input/output bus in response to a failure of any portion of the device controller, and the enable latch is not responsive to the processor module for re-enabling the port. The device controller controls the transfer of information between a processor module and a peripheral device, and information is gated into a register in a port in a device controller in response to a gating signal generated by a processor module. Parity generation and check means continuously monitor parity for the duration of the gating signal.

摘要翻译： 两个或多个单独的处理器模块互连用于并行处理的多处理器系统包括专用于处理器间通信的专用处理器总线。 多处理器系统包括具有多端口设备控制器的输入/输出系统和连接每个设备控制器的输入/输出总线，用于由至少两个不同处理器模块的输入/输出通道进行访问。 每个设备控制器包括一个逻辑，确保一次只选择一个端口进行访问。 每个端口中的启用锁存器动态地禁用该端口在相关输入/输出总线上放置任何信号以响应设备控制器的任何部分的故障，并且使能锁存器不响应于处理器模块以重新启用 港口。 设备控制器控制处理器模块和外围设备之间的信息传送，并且响应于由处理器模块产生的选通信号，将信息选通到设备控制器的端口中的寄存器中。 奇偶校验生成和检查意味着持续监视门控信号的持续时间。

公开(公告)号：US4356550A

公开(公告)日：1982-10-26

申请号：US147305

申请日：1980-05-06

申请人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

发明人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

IPC分类号： G06F11/18 ,  G06F1/26 ,  G06F5/06 ,  G06F7/78 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/28 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173

CPC分类号： G06F7/78 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/2007 ,  G06F11/2015 ,  G06F11/2023 ,  G06F11/2035 ,  G06F11/2043 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/14 ,  G06F12/1458 ,  G06F13/122 ,  G06F13/20 ,  G06F13/287 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F5/06

摘要： A multiprocessor system, the kind in which two or more separate processor modules are interconnected for two power supplies, provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional.The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user program. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system.The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

摘要翻译： 一个多处理器系统，两个或更多个独立的处理器模块相互连接的两个电源的类型，在其他电源出现故障的情况下为设备控制器提供整个电源。 分布式电源系统允许任何处理器模块或设备控制器断电，以便在多处理器系统的其余部分在线和功能的同时，可以在断电状态下进行在线维护。 多处理器系统包括存储器系统，其中每个处理器模块的存储器被分成四个逻辑地址区域 - 用户数据，系统数据，用户代码和系统代码。 存储器系统包括映射，其将逻辑地址转换为物理地址，并且与多处理器系统协作，以将页面从次要存储器引入主要主存储器，以实现虚拟存储器系统。 地图还提供保护功能。 它在多程序环境中为用户提供固有的保护，将程序与数据隔离开来，并保护系统程序免受用户程序的影响。 地图还提供每个逻辑页面的参考历史信息，以帮助操作系统进行高效的内存管理。 多处理器系统在每个处理器模块的存储器中包括错误检测和校正系统，其检测所有单个位和双位错误，并且校正半导体存储器存储器中的所有单个位错误。

公开(公告)号：US4228496A

公开(公告)日：1980-10-14

申请号：US721043

申请日：1976-09-07

申请人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

发明人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

IPC分类号： G06F11/18 ,  G06F1/26 ,  G06F5/06 ,  G06F7/78 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/28 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F15/06

CPC分类号： G06F7/78 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/2007 ,  G06F11/2015 ,  G06F11/2023 ,  G06F11/2035 ,  G06F11/2043 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/14 ,  G06F12/1458 ,  G06F13/122 ,  G06F13/20 ,  G06F13/287 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F5/06

摘要： A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller.The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time.The multiprocessor system includes a distributed power supply system which insures nonstop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional.The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system.The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

公开(公告)号：US4672535A

公开(公告)日：1987-06-09

申请号：US713583

申请日：1985-03-18

申请人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

发明人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

IPC分类号： G06F11/18 ,  G06F1/26 ,  G06F5/06 ,  G06F7/78 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/28 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173

CPC分类号： G06F7/78 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/2007 ,  G06F11/2015 ,  G06F11/2023 ,  G06F11/2035 ,  G06F11/2043 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/14 ,  G06F12/1458 ,  G06F13/122 ,  G06F13/20 ,  G06F13/287 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F5/06

摘要： In a multiprocessor system of the type in which two or more separate processor modules are connected by an interprocessor bus dedicated exclusively to interprocessor communication for parallel processing, there is provided an input/output system having multiported device controllers connected to the multiprocessor system by input/output buses. Each device controller is shared by pairs of the processor modules, and includes logic that ensures that only one port is selected for access at a time.

摘要翻译： 在通过专用于处理器间通信专用于并行处理的处理器间总线将两个或更多个分离的处理器模块连接在一起的多处理器系统中，提供了一种具有多端口设备控制器的输入/输出系统，其通过输入/ 输出总线 每个设备控制器由成对的处理器模块共享，并且包括确保一次只选择一个端口以进行访问的逻辑。

公开(公告)号：US4639864A

公开(公告)日：1987-01-27

申请号：US147135

申请日：1980-05-06

申请人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

发明人： James A. Katzman ,  Joel F. Bartlett ,  Richard M. Bixler ,  William H. Davidow ,  John A. Despotakis ,  Peter J. Graziano ,  Michael D. Green ,  David A. Greig ,  Steven J. Hayashi ,  David R. Mackie ,  Dennis L. McEvoy ,  James G. Treybig ,  Steven W. Wierenga

IPC分类号： G06F11/18 ,  G06F1/26 ,  G06F5/06 ,  G06F7/78 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/28 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173

CPC分类号： G06F7/78 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/2007 ,  G06F11/2015 ,  G06F11/2023 ,  G06F11/2035 ,  G06F11/2043 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/14 ,  G06F12/1458 ,  G06F13/122 ,  G06F13/20 ,  G06F13/287 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F5/06

摘要： A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules.The multiprocessor system includes a distributed power supply system which insures non-stop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. A power interlock system and a method are provided for protection against data corruption.

摘要翻译： 一种多处理器系统，其中两个或多个分离的处理器模块互连用于并行处理。 多处理器系统包括具有多端口设备控制器的输入/输出系统和连接每个设备控制器的输入/输出总线，用于由至少两个不同处理器模块的输入/输出通道进行访问。 多处理器系统包括分布式电源系统，其在系统的一部分电源发生故障的情况下确保多处理器系统的其余部分的不间断操作。 分布式电源系统包括用于每个处理器模块的单独的电源和用于每个设备控制器的两个单独的电源。 提供电源互锁系统和方法来防止数据损坏。