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14 条记录 (耗时 0.015 秒)

    Data streaming mechanism in a microprocessor
    1.
    发明授权
    Data streaming mechanism in a microprocessor 有权
    微处理器中的数据流机制

    公开(公告)号：US06957305B2

    公开(公告)日：2005-10-18

    申请号：US10232248

    申请日：2002-08-29

    申请人： David Scott Ray ,  David J. Shippy

    发明人： David Scott Ray ,  David J. Shippy

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/0859 ,  G06F9/30047 ,  G06F12/0862 ,  G06F12/0897

    摘要： This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level of the cache hierarchy to prefetch data into. A first asynchronous form of a DCBT instruction is issued to prefetch a stream of data into a L2 cache. A second synchronous form of a DCBT instruction is used to prefetch data from the L2 cache to the CRB in the main CPU, which will bypass the L1 data cache and forward data directly to the register file. This CRB has a dual usage and is used to hold both normal cache reloads as well as the aforementioned prefetched cache lines.

    摘要翻译： 本发明提供了一种双重使用高速缓存重载缓冲器（CRB），用于保存需求负载以及预取负载。 数据高速缓存块触摸（DCBT）指令的新形式指定要将数据预取到哪个级别的缓存层次结构。 颁发DCBT指令的第一种异步形式，以将数据流预取到L 2高速缓存中。 DCBT指令的第二种同步形式用于将数据从L 2缓存预取到主CPU中的CRB，这将绕过L 1数据高速缓存并将数据直接转发到寄存器文件。 该CRB具有双重用途，用于保存正常缓存重新加载以及上述预取缓存行。

    Method and system for high performance dynamic and user programmable cache arbitration
    2.
    发明授权
    Method and system for high performance dynamic and user programmable cache arbitration 失效
    高性能动态和用户可编程高速缓存仲裁的方法和系统

    公开(公告)号：US5822758A

    公开(公告)日：1998-10-13

    申请号：US709793

    申请日：1996-09-09

    申请人： Albert John Loper ,  Timothy Alan Elliott ,  Christopher Hans Olson ,  David J. Shippy

    发明人： Albert John Loper ,  Timothy Alan Elliott ,  Christopher Hans Olson ,  David J. Shippy

    IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F12/00

    CPC分类号： G06F12/0897 ,  G06F13/18

    摘要： A system and method for improving arbitration of a plurality of events that may require access to a cache is disclosed. In a first aspect, the method and system provide dynamic arbitration. The first aspect comprises first logic for determining whether at least one of the plurality of events requires access to the cache and for outputting at least one signal in response thereto. Second logic coupled to the first logic determines the priority of each of the plurality of events in response to the at least one signal and outputs a second signal specifying the priority of each event. Third logic coupled to the second logic grants access to the cache in response to the second signal. A second aspect of the method and system provides user programmable arbitration. The second aspect comprises a storage unit which allows the user to input information indicating the priority of at least one of the plurality of events and outputs a first signal in response to the information. In the second aspect, first logic coupled to the storage unit determines the priority of each of the plurality of events in response to the first signal and outputs a second signal indicating the priority of each event. Second logic coupled to the first logic grants access to the cache in response to the second signal.

    摘要翻译： 公开了一种用于改善可能需要访问高速缓存的多个事件的仲裁的系统和方法。 在第一方面，该方法和系统提供动态仲裁。 第一方面包括用于确定多个事件中的至少一个是否需要访问高速缓冲存储器并且响应于此来输出至少一个信号的第一逻辑。 耦合到第一逻辑的第二逻辑响应于至少一个信号确定多个事件中的每一个的优先级，并且输出指定每个事件的优先级的第二信号。 耦合到第二逻辑的第三逻辑响应于第二信号而允许对高速缓存的访问。 该方法和系统的第二方面提供用户可编程仲裁。 第二方面包括存储单元，其允许用户输入指示多个事件中的至少一个的优先级的信息，并且响应于该信息输出第一信号。 在第二方面，耦合到存储单元的第一逻辑响应于第一信号确定多个事件中的每一个的优先级，并且输出指示每个事件的优先级的第二信号。 耦合到第一逻辑的第二逻辑响应于第二信号而允许对高速缓存的访问。

    Power throttling method and apparatus
    3.
    发明授权
    Power throttling method and apparatus 失效
    功率节流方法和装置

    公开(公告)号：US07496776B2

    公开(公告)日：2009-02-24

    申请号：US10645024

    申请日：2003-08-21

    申请人： James Allan Kahle ,  David J. Shippy ,  Albert James Van Norstrand, Jr.

    发明人： James Allan Kahle ,  David J. Shippy ,  Albert James Van Norstrand, Jr.

    IPC分类号： G06F1/32

    CPC分类号： G06F9/30112 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30141 ,  G06F9/30189 ,  Y02D10/171 ,  Y02D50/20

    摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.

    摘要翻译： 公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。 还防止时钟信号被施加到这些未使用的组件。 作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。 用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。 当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。

    POWER THROTTLING APPARATUS
    6.
    发明申请
    POWER THROTTLING APPARATUS 失效
    电力扭力装置

    公开(公告)号：US20090070609A1

    公开(公告)日：2009-03-12

    申请号：US12269997

    申请日：2008-11-13

    申请人： James Allan Kahle ,  David J. Shippy ,  Albert James Van Norstrand, JR.

    发明人： James Allan Kahle ,  David J. Shippy ,  Albert James Van Norstrand, JR.

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F9/30112 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30141 ,  G06F9/30189 ,  Y02D10/171 ,  Y02D50/20

    摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.

    摘要翻译： 公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。 还防止时钟信号被施加到这些未使用的组件。 作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。 用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。 当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。

    Distributed address arbitration scheme for symmetrical multiprocessor system
    7.
    发明授权
    Distributed address arbitration scheme for symmetrical multiprocessor system 失效
    对称多处理器系统的分布式地址仲裁方案

    公开(公告)号：US07484052B2

    公开(公告)日：2009-01-27

    申请号：US11120909

    申请日：2005-05-03

    申请人： Brian M. Bass ,  Thomas L. Jeremiah ,  Charles R. Johns ,  David J. Shippy ,  Thuong Q. Truong

    发明人： Brian M. Bass ,  Thomas L. Jeremiah ,  Charles R. Johns ,  David J. Shippy ,  Thuong Q. Truong

    IPC分类号： G06F12/00

    CPC分类号： G06F12/06

    摘要： The present invention utilizes the good qualities of a single address concentrator (AC), without any extra chips or wires, and distributes the AC function among the various chips, making use of the fact that each chip in the system has a copy of the AC function therein. Using the distributed address concentrator function, each chip will handle approximately one-fourth of the command traffic and the average latency of servicing the commands will be approximately the same across each chip in the system.

    摘要翻译： 本发明利用单个地址集中器（AC）的良好品质，而不需要任何额外的芯片或电线，并且在各种芯片之间分配AC功能，利用系统中的每个芯片具有AC的副本 功能。 使用分布式地址集中器功能，每个芯片将处理大约四分之一的命令流量，并且在系统中的每个芯片上的平均服务延迟将大致相同。

    System and method for identifying and accessing streaming data in a locked portion of a cache
    9.
    发明授权
    System and method for identifying and accessing streaming data in a locked portion of a cache 失效
    用于在高速缓存的锁定部分中识别和访问流数据的系统和方法

    公开(公告)号：US06961820B2

    公开(公告)日：2005-11-01

    申请号：US10366440

    申请日：2003-02-12

    申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David J. Shippy ,  Thuong Quang Truong

    发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David J. Shippy ,  Thuong Quang Truong

    IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/12

    CPC分类号： G06F12/126

    摘要： A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.

    摘要翻译： 提供了一种系统和方法，用于在计算机系统中用高速缓存高效地处理数据。 计算机系统具有处理器，缓存和系统存储器。 处理器发出流数据的数据请求。 流数据具有一个或多个小数据部分。 系统存储器与处理器通信。 系统存储器具有用于存储流数据的特定区域。 缓存耦合到处理器。 高速缓存具有为流数据锁定的预定义区域。 高速缓存控制器耦合到高速缓存，并且与处理器和系统存储器通信，以将流式数据的至少一个小数据部分从系统存储器的特定区域发送到高速缓存的预定义区域 在缓存的预定义区域中没有找到小数据部分。