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    Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides
    4.
    发明授权
    Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides 有权
    具有超薄SOI层和掩埋氧化物的绝缘体上半导体（SOI）衬底

    公开(公告)号：US09059245B2

    公开(公告)日：2015-06-16

    申请号：US13483781

    申请日：2012-05-30

    申请人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76243

    摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.

    摘要翻译： 提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。 使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。 氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。 在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

    Method for controlled removal of a semiconductor device layer from a base substrate
    5.
    发明授权
    Method for controlled removal of a semiconductor device layer from a base substrate 有权
    从基底基板控制去除半导体器件层的方法

    公开(公告)号：US09059073B2

    公开(公告)日：2015-06-16

    申请号：US13603944

    申请日：2012-09-05

    申请人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Norma E. Sosa Cortes

    发明人： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Norma E. Sosa Cortes

    IPC分类号： H01L21/20 ,  H01L21/18 ,  H01L21/78 ,  H01L21/02 ,  H01L31/18

    CPC分类号： H01L21/187 ,  H01L21/02002 ,  H01L21/7813 ,  H01L31/1892 ,  Y02E10/50

    摘要： A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.

    摘要翻译： 提供从基底基板去除半导体器件层的方法，其包括在基底基板的上表面上提供裂纹扩展层。 在裂纹扩展层上形成包括至少一个半导体器件的半导体器件层。 接下来，蚀刻裂纹扩展层的端部以在裂纹扩展层中引发裂纹。 蚀刻的裂纹扩展层然后被切割，以向半导体器件层的表面和另一个裂开的裂纹扩展层部分提供切割的裂纹扩展层部分到基底衬底的上表面。 从半导体器件层的表面去除切割的裂纹扩展层部分，并从基底基板的上表面除去另一个裂开的裂纹扩展层部分。

    Strained silicon and strained silicon germanium on insulator
    8.
    发明授权
    Strained silicon and strained silicon germanium on insulator 有权
    应变硅和应变硅锗绝缘体

    公开(公告)号：US08859348B2

    公开(公告)日：2014-10-14

    申请号：US13544093

    申请日：2012-07-09

    申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Devendra K. Sadana

    IPC分类号： H01L21/84

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

    摘要： A method for fabricating field effect transistors patterns a strained silicon layer formed on a dielectric layer of a substrate into at least one NFET region including at least a first portion of the strained silicon layer. The strained silicon layer is further patterned into at least one PFET region including at least a second portion of the strained silicon layer. A masking layer is formed over the first portion of the strained silicon layer. After the masking layer has been formed, the second strained silicon layer is transformed into a relaxed silicon layer. The relaxed silicon layer is transformed into a strained silicon germanium layer.

    摘要翻译： 用于制造场效应晶体管的方法将形成在衬底的电介质层上的应变硅层图案化成至少一个包括应变硅层的第一部分的NFET区域。 将应变硅层进一步图案化成至少一个包括应变硅层的至少第二部分的PFET区域。 在应变硅层的第一部分上形成掩模层。 在形成掩模层之后，将第二应变硅层转变成松弛的硅层。 松弛的硅层被转变成应变硅锗层。

    STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR
    9.
    发明申请
    STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR 有权
    绝缘体上的应变硅和应变硅锗

    公开(公告)号：US20140008729A1

    公开(公告)日：2014-01-09

    申请号：US13615016

    申请日：2012-09-13

    申请人： Stephen W. BEDELL ,  Kangguo CHENG ,  Bruce DORIS ,  Ali KHAKIFIROOZ ,  Devendra K. SADANA

    发明人： Stephen W. BEDELL ,  Kangguo CHENG ,  Bruce DORIS ,  Ali KHAKIFIROOZ ,  Devendra K. SADANA

    IPC分类号： H01L21/336 ,  H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

    摘要： A structure includes a tensilely strained nFET region including a strained silicon layer of a silicon on insulator wafer. A relaxed nFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer. A compressively strained pFET region includes a SiGe layer which was converted from a tensilely strained silicon layer of the silicon on insulator wafer. A relaxed pFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer.

    摘要翻译： 一种结构包括包括绝缘体硅晶片的应变硅层的拉伸应变nFET区域。 松弛的nFET区域包括离子注入硅和绝缘体硅晶片的拉伸应变硅层的离子注入二氧化硅界面层之一。 压缩应变pFET区域包括从绝缘体硅晶片的拉伸应变硅层转换的SiGe层。 松弛的pFET区域包括离子注入硅和绝缘硅晶片上的拉伸应变硅层的离子注入二氧化硅界面层之一。