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    MAGNESIUM MODIFIED ULTRA-STABLE RARE EARTH Y-TYPE MOLECULAR SIEVE AND PREPARATION METHOD THEREFOR
    2.
    发明申请
    MAGNESIUM MODIFIED ULTRA-STABLE RARE EARTH Y-TYPE MOLECULAR SIEVE AND PREPARATION METHOD THEREFOR 有权
    镁改性超稳定稀土Y型分子筛及其制备方法

    公开(公告)号：US20150175432A1

    公开(公告)日：2015-06-25

    申请号：US14365432

    申请日：2012-04-13

    申请人： Xionghou Gao ,  Haitao Zhang ,  Hongchang Duan ,  Chaowei Liu ,  Di Li ,  Xueli Li ,  Zhengguo Tan ,  Yunfeng Zheng ,  Xiaoliang Huang ,  Jinjun Cai ,  Chenxi Zhang

    发明人： Xionghou Gao ,  Haitao Zhang ,  Hongchang Duan ,  Chaowei Liu ,  Di Li ,  Xueli Li ,  Zhengguo Tan ,  Yunfeng Zheng ,  Xiaoliang Huang ,  Jinjun Cai ,  Chenxi Zhang

    IPC分类号： C01B39/24 ,  B01J29/08 ,  B01J37/08 ,  C01B39/02

    CPC分类号： C01B39/24 ,  B01J29/084 ,  B01J29/088 ,  B01J29/80 ,  B01J35/023 ,  B01J35/10 ,  B01J35/109 ,  B01J37/08 ,  B01J37/30 ,  B01J2229/18 ,  B01J2229/186 ,  B01J2229/40 ,  B01J2229/42 ,  C01B39/026 ,  C10G11/05

    摘要： The present invention provides a magnesium-modified ultra-stable rare earth type Y molecular sieve and the preparation method thereof, which method is carried out by subjecting a NaY molecular sieve as the raw material to a rare earth exchange and a dispersing pre-exchange, then to an ultra-stabilization calcination treatment, and finally to a magnesium modification. The molecular sieve comprises 0.2 to 5% by weight of magnesium oxide, 1 to 20% by weight of rare earth oxide, and not more than 1.2% by weight of sodium oxide, and has a crystallinity of 46 to 63%, and a lattice parameter of 2.454 nm to 2.471 nm. In contrast to the prior art, in the molecular sieve prepared by this method, rare earth ions are located in sodalite cages, which is demonstrated by the fact that no rare earth ion is lost during the reverse exchange process. Moreover, the molecular sieve prepared by such a method has a molecular particle size D(v,0.5) of not more than 3.0 μm and a D(v,0.9) of not more than 20 μm. Such a molecular sieve has both high stability and high selectivity for the target product, while cracking catalysts using the molecular sieve as an active component is characterized by a high heavy-oil-conversion capacity and a high yield of valuable target products.

    摘要翻译： 本发明提供一种镁改性超稳定稀土类Y分子筛及其制备方法，该方法是以NaY分子筛为原料进行稀土交换和分散预交换， 然后进行超稳定化煅烧处理，最后进行镁改性。 分子筛含有0.2〜5重量％的氧化镁，1〜20重量％的稀土氧化物和1.2重量％的氧化钠，结晶度为46〜63％，晶格 参数为2.454 nm至2.471 nm。 与现有技术相反，在通过该方法制备的分子筛中，稀土离子位于钠盐网箱中，这通过在反向交换过程中没有稀土离子损失的事实来证明。 此外，通过这种方法制备的分子筛具有不大于3.0μm的分子粒度D（v，0.5）和不大于20μm的D（v，0.9）。 这种分子筛对于目标产物具有高稳定性和高选择性，而使用分子筛作为活性组分的裂化催化剂的特征在于高重油转化能力和高产率的有价值的目标产物。

    Floating body field-effect transistors, and methods of forming floating body field-effect transistors
    4.
    发明授权
    Floating body field-effect transistors, and methods of forming floating body field-effect transistors 有权
    浮体场效应晶体管，以及形成浮体场效应晶体管的方法

    公开(公告)号：US08395214B2

    公开(公告)日：2013-03-12

    申请号：US13088531

    申请日：2011-04-18

    申请人： Jun Liu ,  Di Li ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch

    发明人： Jun Liu ,  Di Li ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/02

    CPC分类号： H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

    摘要翻译： 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

    Nand flash memory programming
    5.
    发明申请
    Nand flash memory programming 有权
    Nand闪存编程

    公开(公告)号：US20080025097A1

    公开(公告)日：2008-01-31

    申请号：US11495507

    申请日：2006-07-28

    申请人： Seiichi Aritome ,  Haitao Liu ,  Di Li

    发明人： Seiichi Aritome ,  Haitao Liu ,  Di Li

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12

    摘要： A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.

    摘要翻译： 用于防止短沟道源侧选择栅极结构中的穿通的编程方法和存储器结构包括调整所选择和未选择的位线上的电压以及编程，通过和选择栅极电压。

    METHOD OF FORMING MEMORY DEVICES BY PERFORMING HALOGEN ION IMPLANTATION AND DIFFUSION PROCESSES
    6.
    发明申请
    METHOD OF FORMING MEMORY DEVICES BY PERFORMING HALOGEN ION IMPLANTATION AND DIFFUSION PROCESSES 有权
    通过实施卤素离子植入和扩散过程形成记忆体装置的方法

    公开(公告)号：US20080014698A1

    公开(公告)日：2008-01-17

    申请号：US11457620

    申请日：2006-07-14

    申请人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

    发明人： Kirk Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

    摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

    摘要翻译： 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺，以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

    FLASH MEMORY DEVICE WITH ENLARGED CONTROL GATE STRUCTURE, AND METHODS OF MAKING SAME
    7.
    发明申请
    FLASH MEMORY DEVICE WITH ENLARGED CONTROL GATE STRUCTURE, AND METHODS OF MAKING SAME 审中-公开
    具有扩大控制门结构的闪存存储器件及其制造方法

    公开(公告)号：US20070228450A1

    公开(公告)日：2007-10-04

    申请号：US11277823

    申请日：2006-03-29

    申请人： Di Li ,  Chandra Mouli

    发明人： Di Li ,  Chandra Mouli

    IPC分类号： H01L29/788 ,  H01L21/8238

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： Disclosed is a flash memory device with an enlarged control gate structure, and various methods of make same. In one illustrative embodiment, the device includes a plurality of floating gate structures formed above a semiconducting substrate, an isolation structure positioned between each of the plurality of floating gate structures and a control gate structure comprising a plurality of enlarged end portions, each of the enlarged end portions being positioned between adjacent floating gate structures.

    摘要翻译： 公开了一种具有扩大的控制栅极结构的闪速存储器件，以及各种制造方法。 在一个说明性实施例中，该器件包括形成在半导体衬底之上的多个浮动栅极结构，位于多个浮动栅极结构中的每一个之间的隔离结构和包括多个扩大端部的控制栅极结构， 端部位于相邻的浮栅结构之间。