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    WAFER ARRANGEMENT AND A METHOD FOR MANUFACTURING THE WAFER ARRANGEMENT
    1.
    发明申请
    WAFER ARRANGEMENT AND A METHOD FOR MANUFACTURING THE WAFER ARRANGEMENT 有权
    WAFER安排和制造WAFER安排的方法

    公开(公告)号：US20100219496A1

    公开(公告)日：2010-09-02

    申请号：US12665876

    申请日：2007-08-08

    申请人： Qingxin Zhang ,  Guo-Qiang Patrick Lo ,  Mingbin Yu ,  Dim-Lee Kwong

    发明人： Qingxin Zhang ,  Guo-Qiang Patrick Lo ,  Mingbin Yu ,  Dim-Lee Kwong

    IPC分类号： H01L31/02

    CPC分类号： B81C3/002 ,  B81C2203/051

    摘要： The wafer arrangement (100) provided comprises a first wafer (101), which comprises an integrated circuit and a recess (105). The wafer arrangement further comprises a portion of a second wafer (103), which comprises a carrier portion and a protrusion (107), the protrusion comprising an active component or actively controlled component (109) such as a MEMS component, wherein the portion of the second wafer (103) is coupled to the first wafer (101) such that the protrusion (107) is received in the recess (105). The invention provides a mechanism for accurately aligning an active component (109) on the second wafer (103) with components on the first wafer (101), such as photonic, electronic or optical components.

    摘要翻译： 提供的晶片装置（100）包括第一晶片（101），其包括集成电路和凹部（105）。 晶片装置还包括第二晶片（103）的一部分，其包括载体部分和突起（107），所述突起包括有源部件或诸如MEMS部件的主动控制部件（109），其中，部分 第二晶片（103）被耦合到第一晶片（101），使得突起（107）被容纳在凹部（105）中。 本发明提供了一种用于将第二晶片（103）上的有源元件（109）与第一晶片（101）上的元件（例如光子，电子或光学元件）精确对准的机构。

    CMOS transistor design for shared N+/P+ electrode with enhanced device performance
    3.
    发明授权
    CMOS transistor design for shared N+/P+ electrode with enhanced device performance 有权
    CMOS晶体管设计用于共享的N + / P +电极，具有增强的器件性能

    公开(公告)号：US06252283B1

    公开(公告)日：2001-06-26

    申请号：US09234855

    申请日：1999-01-22

    申请人： Mark I. Gardner ,  Dim-Lee Kwong ,  Frederick N. Hause

    发明人： Mark I. Gardner ,  Dim-Lee Kwong ,  Frederick N. Hause

    IPC分类号： H01L2701

    CPC分类号： H01L21/28035 ,  H01L21/823842 ,  H01L21/84

    摘要： An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate dielectric layer on the substrate and forming a gate electrode on the gate dielectric layer with a lower surface, a midpoint, and a quantity of p-type impurity. A quantity of nitrogen is introduced into the gate electrode whereby the quantity nitrogen has a peak concentration proximate the lower surface. A quantity of germanium is introduced into the gate electrode and first and second source/drain regions are formed in the substrate. The method enables simultaneous formation of n-channel and p-channel gate electrodes with work functions tailored for both types of devices.

    摘要翻译： 提供集成电路及其制造晶体管的方法。 在一个方面，该方法包括以下步骤：在衬底上形成栅极电介质层，并在具有下表面，中点和一定量的p型杂质的栅极电介质层上形成栅电极。 一定量的氮气被引入到栅极中，由此氮气的量值接近下表面。 将一定数量的锗引入栅电极中，并且在衬底中形成第一和第二源/漏区。 该方法能够同时形成具有为两种类型的器件定制的工作功能的n沟道和p沟道栅电极。

    Semiconductor topography employing a nitrogenated shallow trench isolation structure
    4.
    发明授权
    Semiconductor topography employing a nitrogenated shallow trench isolation structure 有权
    半导体地形采用氮化浅沟槽隔离结构

    公开(公告)号：US06218720B1

    公开(公告)日：2001-04-17

    申请号：US09176131

    申请日：1998-10-21

    申请人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford, Jr.

    发明人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford, Jr.

    IPC分类号： H01L2900

    CPC分类号： H01L21/76224 ,  H01L21/3145 ,  H01L21/3185

    摘要： A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A liner that primarily comprises nitride is formed upon the trench floor and sidewalls. The liner is then oxidized. A trench dielectric may be formed within the trench and planarized to complete the isolation structure.

    摘要翻译： 提出了一种用于制造集成电路的方法，其中在半导体衬底的场区域中对沟槽进行构图。 沟槽通过沟槽底板和沟槽侧壁限定在半导体衬底的内部。 主要包括氮化物的衬垫形成在沟槽底板和侧壁上。 然后将衬里氧化。 沟槽电介质可以形成在沟槽内并且被平坦化以完成隔离结构。

    High K integration of gate dielectric with integrated spacer formation for high speed CMOS
    5.
    发明授权
    High K integration of gate dielectric with integrated spacer formation for high speed CMOS 有权
    高K集成栅极电介质与高速CMOS的集成间隔物形成

    公开(公告)号：US06207995B1

    公开(公告)日：2001-03-27

    申请号：US09255917

    申请日：1999-02-23

    申请人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford

    发明人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford

    IPC分类号： H01L2976

    CPC分类号： H01L21/28194 ,  H01L29/42368 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/78391

    摘要： An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate insulating layer on the substrate with a first outwardly tapered sidewall and a second outwardly tapered sidewall. A gate electrode is formed on the gate insulating layer. A first source/drain region and a second source/drain region are formed in the substrate by implanting ions into the substrate, wherein a first portion of the ions passes through the first sidewall and a second portion of the ions passes through the second sidewall. The method provides for incorporation of spacer-like structure into a gate dielectric layer. Conventional spacer fabrication may be eliminated and graded source/drain regions established with a single implant.

    摘要翻译： 提供集成电路及其制造晶体管的方法。 在一个方面，该方法包括以下步骤：在衬底上形成具有第一向外锥形侧壁和第二向外渐缩侧壁的栅极绝缘层。 在栅极绝缘层上形成栅电极。 通过将离子注入衬底而在衬底中形成第一源/漏区和第二源极/漏极区，其中离子的第一部分穿过第一侧壁，并且离子的第二部分通过第二侧壁。 该方法提供了将间隔物结构结合到栅介质层中。 可以消除传统的间隔物制造，并用单个植入物建立分级的源极/漏极区域。

    Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region
    6.
    发明授权
    Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region 失效
    集成电路器件具有电介质周边区域大于介电中心区域的电容器

    公开(公告)号：US6115233A

    公开(公告)日：2000-09-05

    申请号：US673655

    申请日：1996-06-28

    申请人： John J. Seliskar ,  Derryl D. J. Allman ,  John W. Gregory ,  James P. Yakura ,  Dim Lee Kwong

    发明人： John J. Seliskar ,  Derryl D. J. Allman ,  John W. Gregory ,  James P. Yakura ,  Dim Lee Kwong

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/423 ,  H01G4/005 ,  H01G4/228

    CPC分类号： H01L28/40 ,  H01L27/0688 ,  H01L29/42324

    摘要： The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor. The top electrode is thus disposed above a central region which remains of the dielectric layer and between a peripheral region which remains of the dielectric layer.

    摘要翻译： 本发明涉及半导体器件，优选电容器及其形成方法。 该方法在制造过程中仅增加了一个额外的掩蔽步骤，并且减少了与各种层的对准有关的问题。 在底部电极上形成相对较厚的绝缘层。 具有使用掩模在绝缘层中蚀刻以暴露底部电极的一部分的侧壁的开口。 一旦去除了掩模，然后在包括侧壁的整个结构上依次沉积介电层和导电层。 此后，使用化学机械抛光来去除导电层和电介质层的部分，使得保留的导电层和电介质层形成例如集成电路电容器的顶部电极和电介质层。 因此，顶部电极设置在保留电介质层的中心区域之间以及保留在电介质层的外围区域之间。

    Method for achieving a highly reliable oxide film
    7.
    发明授权
    Method for achieving a highly reliable oxide film 失效
    实现高可靠性氧化膜的方法

    公开(公告)号：US5591681A

    公开(公告)日：1997-01-07

    申请号：US253771

    申请日：1994-06-03

    申请人： Dirk J. Wristers ,  Dim-Lee Kwong ,  H. Jim Fulford, Jr.

    发明人： Dirk J. Wristers ,  Dim-Lee Kwong ,  H. Jim Fulford, Jr.

    IPC分类号： C23C16/56 ,  H01L21/28 ,  H01L21/318 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/3115

    CPC分类号： H01L21/28185 ,  C23C16/56 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/518 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  Y10S438/909 ,  Y10S438/954

    摘要： High quality oxides utilized in tunnel oxides and CMOS gate oxides are formed using a process that includes annealing a semiconductor substrate, after the oxide has been formed, in an ambient comprised of NO to form a surface layer in the oxide containing a concentration of nitrogen. A high-quality tunnel oxide, suitable for EEPROM devices, is formed upon a surface region of a semiconductor body over a heavily-doped N+ layer by first oxidizing the semiconductor body to form an oxide upon the surface region of the semiconductor body over the heavily-doped N+ layer. Next, the semiconductor body is annealed, under a gettering ambient, to densify the oxide and to dope the oxide at its surface and for a portion thereinto near its surface with a gettering agent. The semiconductor body is then oxidized, under an oxidizing ambient, to thicken the oxide. The annealing step in NO improves characteristics for both the gate and tunnel oxides of the device at a temperature substantially reduced from prior art methods and in an ambient atmosphere containing significantly more NO. The NO anneal can be performed in a variety of ways including an RTP anneal, a furnace anneal and can be performed on processes where the oxides are formed using CVD and PECVD.

    摘要翻译： 在隧道氧化物和CMOS栅极氧化物中使用的高质量氧化物使用包括在形成氧化物的氧化物在由NO组成的环境中退火半导体衬底以在含有一定浓度的氮的氧化物中形成表面层的工艺来形成。 通过首先氧化半导体体以在半导体主体的表面区域上形成氧化物，在重掺杂的N +层上的半导体本体的表面区域上形成适用于EEPROM器件的高品质隧道氧化物， 掺杂的N +层。 接下来，在吸气环境下，将半导体本体退火以使氧化物致密化并在其表面上掺杂氧化物，并在其表面附近用吸杂剂掺杂一部分。 然后在氧化环境下氧化半导体体，使氧化物变稠。 NO中的退火步骤在从现有技术方法显着降低的温度下和在含有显着更多的NO的环境气氛中改善器件的栅极和隧道氧化物的特性。 NO退火可以以各种方式进行，包括RTP退火，炉退火，并且可以在使用CVD和PECVD形成氧化物的工艺上进行。