公开(公告)号：US20130308656A1

公开(公告)日：2013-11-21

申请号：US13471613

申请日：2012-05-15

申请人： Moshe Malkin ,  Dimitry Taich ,  Jose Tellado

发明人： Moshe Malkin ,  Dimitry Taich ,  Jose Tellado

IPC分类号： H04J3/02 ,  H04J1/08

CPC分类号： H04L5/06 ,  H04L27/2614 ,  H04L27/2615 ,  H04L27/2618 ,  H04L27/2621

摘要： Embodiments of methods, apparatuses, and systems for signal processing of multiple input signals to control peak amplitudes of a combined signal are disclosed. One method includes receiving a plurality of input signals, generating a combined signal, the combined signal comprising a plurality of sub-channels, wherein each sub-channel includes a representation of at least a portion of at least one of the plurality of input signals, and processing the representation of the least a portion of the at least one of the plurality of input signals of at least one of the sub-channels, to reduce a peak-to-average-power ratio (PAR) of the combined signal.

摘要翻译： 公开了用于信号处理多个输入信号以控制组合信号的峰值幅度的方法，装置和系统的实施例。 一种方法包括接收多个输入信号，产生组合信号，所述组合信号包括多个子信道，其中每个子信道包括所述多个输入信号中的至少一个的至少一部分的表示， 以及处理所述子信道中的至少一个子信道的所述多个输入信号中的至少一个输入信号的至少一部分的表示，以减小所述组合信号的峰值与平均功率比（PAR）。

公开(公告)号：US20110074592A1

公开(公告)日：2011-03-31

申请号：US12960481

申请日：2010-12-04

申请人： Dimitry Taich ,  Jose Tellado

发明人： Dimitry Taich ,  Jose Tellado

IPC分类号： G08B21/00

CPC分类号： H04L7/0083 ,  H04L7/10

摘要： An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the electronic circuitry is deactivated by periodically exchanging synchronization test patterns. At least one of the first data port and the second data port transmit an alert to the other of the first and second data port when data for communication is detected. The other of the first data port and the second data port activate electronic circuitry upon receiving the alert. At least one of the first data port and the second data port transmit data.

摘要翻译： 公开了一种控制通信系统的数据端口的电子电路的激活的装置和方法。 一种方法包括检测用于传输到第二数据端口的数据不足的第一数据端口。 在检测到数据不足时，第一数据端口和第二数据端口中的至少一个解除了第一和第二数据端口中的至少一个的电子电路。 第一和第二数据端口通过周期性地交换同步测试模式而使电子电路停用，从而保持彼此的同步。 当检测到用于通信的数据时，第一数据端口和第二数据端口中的至少一个向第一和第二数据端口中的另一个发送警报。 第一数据端口和第二数据端口中的另一个在接收到警报时激活电子电路。 第一数据端口和第二数据端口中的至少一个发送数据。

公开(公告)号：US07167883B2

公开(公告)日：2007-01-23

申请号：US10320767

申请日：2002-12-16

申请人： Israel Greiss ,  Baruch Bublil ,  Jeffrey Jacob ,  Dimitry Taich

发明人： Israel Greiss ,  Baruch Bublil ,  Jeffrey Jacob ,  Dimitry Taich

IPC分类号： G06F17/10 ,  H03H7/03

CPC分类号： H04B1/0003 ,  H04L1/0054 ,  H04L5/16 ,  H04L7/0004 ,  H04L7/0029 ,  H04L7/0058 ,  H04L7/007 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/14 ,  H04L2025/0349 ,  H04L2025/03617

摘要： A finite impulse response filter, including a plurality of taps arranged to receive and process a sequence of input data samples so as to generate a filter output. Each tap consists of a multiplier operating in one's complement arithmetic, the multiplier being coupled to multiply a respective input sample from the sequence by a respective equalization coefficient, and an adder, which sums an output from the multiplier. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The filter also includes an adjustment-accumulator coupled to receive the filter output and responsive thereto to generate an adjustment that is adapted to correct the filter output to a twos complement result, and an adjustment-adder which sums the adjustment and the filter output to generate a final output.

摘要翻译： 一种有限脉冲响应滤波器，包括多个抽头，其布置成接收和处理一系列输入数据样本以产生滤波器输出。 每个抽头包括以补码运算运算的乘法器，该乘法器被耦合以将来自该序列的相应输入采样乘以相应的均衡系数，以及将来自乘法器的输出相加的加法器。 抽头按顺序排列，使得除序列中的第一次抽头之外的每个抽头的输入样本相对于序列中的先前抽头而被延迟。 滤波器还包括耦合以接收滤波器输出并对其进行响应的调整 - 累加器，以产生适于将滤波器输出校正为二进制补码结果的调整，以及调整加法器，其将调整和滤波器输出相加以产生 最终输出。

公开(公告)号：US20110051620A1

公开(公告)日：2011-03-03

申请号：US12941039

申请日：2010-11-06

申请人： Dimitry Taich ,  Jose Tellado

发明人： Dimitry Taich ,  Jose Tellado

IPC分类号： H04L12/26

CPC分类号： H04L12/10

摘要： An apparatuses and methods of setting power back-off of a master transceiver and a slave transceiver is disclosed. One example of a method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off. One example of an apparatus includes a master transceiver and slave transceiver system. The slave transceiver is connected to the master transceiver through a cable. The master transceiver includes means for determining a master power back-off. The slave transceiver includes means for determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

摘要翻译： 公开了一种设置主收发器和从属收发器的功率回退的装置和方法。 方法的一个示例包括主收发器确定主功率回退，并且从收发器基于从主收发器接收的信号以及基于主功率回退确定从功率回退。 设备的一个示例包括主收发器和从收发器系统。 从设备收发器通过电缆连接到主收发器。 主收发器包括用于确定主功率回退的装置。 从属收发器包括用于基于从主收发器接收的信号以及基于主功率回退确定从功率回退的装置。

公开(公告)号：US07860020B2

公开(公告)日：2010-12-28

申请号：US11438177

申请日：2006-05-22

申请人： Dimitry Taich ,  Jose Tellado

发明人： Dimitry Taich ,  Jose Tellado

IPC分类号： H04L12/26 ,  H04B1/44

CPC分类号： H04L12/10

摘要： An apparatus and method of setting power back-off of a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

摘要翻译： 公开了一种设置主收发器和从属收发器的功率回退的装置和方法。 该方法包括主收发器确定主功率回退，并且从收发器基于从主收发器接收的信号确定从属功率回退，并且基于主功率回退。

公开(公告)号：US20080049818A1

公开(公告)日：2008-02-28

申请号：US11510934

申请日：2006-08-28

申请人： Dimitry Taich ,  Jose Tellado

发明人： Dimitry Taich ,  Jose Tellado

IPC分类号： H04L5/16

CPC分类号： H04B1/406

摘要： A method and apparatus for receiving one of a plurality of Ethernet transmission protocol signals is disclosed. Each transmission protocol signal includes a plurality of transmission signal streams. The method includes determining which of the transmission protocol signals is being received. An analog front-end processor is connected to one of a plurality of protocol digital processors based on the transmission protocol signal being received. A setting of at least one functional parameter of the analog front-end processor and/or the protocol digital processors is selected based on the transmission protocol signal being received. A sampling rate of the analog front-end processor and/or a processing rate of the protocol digital processors are selected based on the transmission protocol signal being received. The plurality of transmission signal streams of the transmission protocol signal being received by the analog front-end processor are ADC sampled based on a shared clock source.

摘要翻译： 公开了一种用于接收多个以太网传输协议信号之一的方法和装置。 每个传输协议信号包括多个传输信号流。 该方法包括确定正在接收哪些传输协议信号。 模拟前端处理器基于所接收的传输协议信号连接到多个协议数字处理器之一。 基于正在接收的传输协议信号来选择模拟前端处理器和/或协议数字处理器的至少一个功能参数的设置。 基于正在接收的传输协议信号来选择模拟前端处理器的采样率和/或协议数字处理器的处理速率。 由模拟前端处理器接收的传输协议信号的多个发送信号流基于共享时钟源进行ADC采样。

公开(公告)号：US08321708B2

公开(公告)日：2012-11-27

申请号：US12384298

申请日：2009-04-02

申请人： John Dring ,  Jose Tellado ,  Dimitry Taich

发明人： John Dring ,  Jose Tellado ,  Dimitry Taich

IPC分类号： G06F1/32 ,  G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3209

摘要： An apparatus and method of interfacing physical layer (PHY) control with media access control (MAC) is disclosed. One method includes signaling to the PHY control to operate in a low-power mode when the MAC is detected to be transmitting idle patterns. The MAC transitioning from transmitting the idle patterns to transmitting data can be detected. When the transition is detected, the PHY control is signaled to transition to a wake up mode. Data from the MAC is buffered while the PHY control is in the wake up mode. The buffered data is provided to the PHY control after the PHY control has completed the wake up mode.

摘要翻译： 公开了将物理层（PHY）控制与媒体访问控制（MAC）接口的装置和方法。 当检测到MAC被发送空闲模式时，一种方法包括向PHY控制器发送信令以在低功率模式下操作。 可以检测从发送空闲模式到发送数据的MAC转换。 当检测到转换时，发送PHY控制以转换到唤醒模式。 当PHY控制处于唤醒模式时，来自MAC的数据被缓冲。 在PHY控制完成唤醒模式之后，将缓冲的数据提供给PHY控制。

公开(公告)号：US07782929B2

公开(公告)日：2010-08-24

申请号：US11510934

申请日：2006-08-28

申请人： Dimitry Taich ,  Jose Tellado

发明人： Dimitry Taich ,  Jose Tellado

IPC分类号： H04B1/38 ,  H04L5/16

CPC分类号： H04B1/406

摘要： A method and apparatus for receiving one of a plurality of Ethernet transmission protocol signals is disclosed. Each transmission protocol signal includes a plurality of transmission signal streams. The method includes determining which of the transmission protocol signals is being received. An analog front-end processor is connected to one of a plurality of protocol digital processors based on the transmission protocol signal being received. A setting of at least one functional parameter of the analog front-end processor and/or the protocol digital processors is selected based on the transmission protocol signal being received. A sampling rate of the analog front-end processor and/or a processing rate of the protocol digital processors are selected based on the transmission protocol signal being received. The plurality of transmission signal streams of the transmission protocol signal being received by the analog front-end processor are ADC sampled based on a shared clock source.

摘要翻译： 公开了一种用于接收多个以太网传输协议信号之一的方法和装置。 每个传输协议信号包括多个传输信号流。 该方法包括确定正在接收哪些传输协议信号。 模拟前端处理器基于所接收的传输协议信号连接到多个协议数字处理器之一。 基于正在接收的传输协议信号来选择模拟前端处理器和/或协议数字处理器的至少一个功能参数的设置。 基于正在接收的传输协议信号来选择模拟前端处理器的采样率和/或协议数字处理器的处理速率。 由模拟前端处理器接收的传输协议信号的多个发送信号流基于共享时钟源进行ADC采样。

公开(公告)号：US20100104056A1

公开(公告)日：2010-04-29

申请号：US12290181

申请日：2008-10-28

申请人： Dimitry Taich ,  Jose Tellado

发明人： Dimitry Taich ,  Jose Tellado

IPC分类号： H04L7/02

CPC分类号： H04L7/0083 ,  H04L7/10

摘要： An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the electronic circuitry is deactivated by periodically exchanging synchronization test patterns. At least one of the first data port and the second data port transmit an alert to the other of the first and second data port when data for communication is detected. The other of the first data port and the second data port activate electronic circuitry upon receiving the alert. At least one of the first data port and the second data port transmit data.

摘要翻译： 公开了一种控制通信系统的数据端口的电子电路的激活的装置和方法。 一种方法包括检测用于传输到第二数据端口的数据不足的第一数据端口。 在检测到数据不足时，第一数据端口和第二数据端口中的至少一个解除了第一和第二数据端口中的至少一个的电子电路。 第一和第二数据端口通过周期性地交换同步测试模式而使电子电路停用，从而保持彼此的同步。 当检测到用于通信的数据时，第一数据端口和第二数据端口中的至少一个向第一和第二数据端口中的另一个发送警报。 第一数据端口和第二数据端口中的另一个在接收到警报时激活电子电路。 第一数据端口和第二数据端口中的至少一个发送数据。

公开(公告)号：US07170931B2

公开(公告)日：2007-01-30

申请号：US10320771

申请日：2002-12-16

申请人： Israel Greiss ,  Baruch Bublil ,  Jeffrey Jacob ,  Dimitry Taich

发明人： Israel Greiss ,  Baruch Bublil ,  Jeffrey Jacob ,  Dimitry Taich

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04B1/0003 ,  H04L1/0054 ,  H04L5/16 ,  H04L7/0004 ,  H04L7/0029 ,  H04L7/0058 ,  H04L7/007 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/14 ,  H04L2025/0349 ,  H04L2025/03617

摘要： An equalizer, consisting of a plurality of taps, each tap having a multiplier which is coupled to multiply a respective input sample by a respective coefficient, the taps being arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence.The equalizer further includes an input selector, which is coupled to toggle the input sample to at least a selected tap among the plurality of taps, responsive to a state of the equalizer, so that the equalizer operates in a first state as a feed forward equalizer, and in a second state as a blind equalizer.

摘要翻译： 一个由多个抽头组成的均衡器，每个抽头具有一个乘法器，该乘法器被耦合以将相应的输入采样乘以相应的系数，该抽头按顺序排列，使得每个抽头的输入样本除了第一个 按顺序点击，相对于序列中的先前轻敲延迟。 均衡器还包括输入选择器，其响应于均衡器的状态而被耦合以将输入采样触发到多个抽头中的至少一个选择的抽头，使得均衡器在第一状态下操作为前馈均衡器 ，并且处于作为盲均衡器的第二状态。