公开(公告)号：US08536925B2

公开(公告)日：2013-09-17

申请号：US12598352

申请日：2008-12-29

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Jeffrey J. Nagy ,  Peter J. Nicholas

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Jeffrey J. Nagy ,  Peter J. Nicholas

IPC分类号： H03L5/00

CPC分类号： H03K3/356113 ,  H03K3/0375

摘要： A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).

摘要翻译： 电压转换器电路（320）包括适于接收参考第一电压源（VDD核心）的输入信号的输入级（322），适于连接到第二电压源（VDD33）的锁存器（326） 至少临时存储输入信号的逻辑状态，以及耦合在输入级（322）和锁存器（326）之间的电压钳位（324）。 电压钳（322）用于将锁存器（326）两端的最大电压设定为第一规定电平，并将输入级两端的最大电压设定为第二规定电平。 电压转换器电路（320）在闩锁（326）和电压钳（324）之间的连接处产生第一输出信号（II）。 电压转换器电路在电压钳位器（324）和输入级（322）之间的接点处产生第二输出信号（15）。

公开(公告)号：US07936209B2

公开(公告)日：2011-05-03

申请号：US12428556

申请日：2009-04-23

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H03K17/0822 ,  H03K19/018528

摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

摘要翻译： 所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。 第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。 第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。 从缓冲器的工作电压产生第一和第二偏置电压。 从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压 缓冲。 第三和第四偏置电压分别提供给第一和第二过压保护电路。

公开(公告)号：US07529071B2

公开(公告)日：2009-05-05

申请号：US11535719

申请日：2006-09-27

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

IPC分类号： H02H3/22

CPC分类号： H03K17/063

摘要： A circuit for selectively bypassing a capacitive element includes at least one NMOS device selectively connectable across the capacitive element to be bypassed, and at least first and second PMOS devices. The PMOS devices are selectively connectable together in series across the capacitive element to be bypassed. The NMOS device provides a first bypass path and the first and second PMOS devices collectively provide a second bypass path.

摘要翻译： 用于选择性地绕过电容元件的电路包括至少一个可选择地连接在待旁路的电容元件上的NMOS器件，以及至少第一和第二PMOS器件。 PMOS器件可选择性地连接在电容元件上串联在一起以被旁路。 NMOS器件提供第一旁路路径，并且第一和第二PMOS器件共同提供第二旁路路径。

公开(公告)号：US07529070B2

公开(公告)日：2009-05-05

申请号：US11076850

申请日：2005-03-11

申请人： Dipankar Bhattacharya ,  John Kriz ,  Che Coi Leung ,  Duane J. Loeper ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  John Kriz ,  Che Coi Leung ,  Duane J. Loeper ,  Yehuda Smooha

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： An ESD clamp circuit for use between separate power rails. An ESD clamp is based on a wide nMOSFET. A symmetrical circuit is designed vis-à-vis the two power rails, with respect to ground, allowing discharge of an ESD surge in both polarities of stress. An nMOSFET device drives the gate of a large nMOSFET (e.g., having a device width between 1000 and 10,000 microns). The large power rail-to-power rail nMOSFET has its gate controlled by the output inverter stage of either ESD detection circuit connected to a respective power supply rail. The gate is switched to a common ground during normal operation of the integrated circuit.

摘要翻译： 用于单独电源轨之间的ESD钳位电路。 ESD钳位基于宽nMOSFET。 相对于地面，相对于两个电源轨设计了对称电路，允许在两个极限应力下放电ESD浪涌。 nMOSFET器件驱动大的nMOSFET的栅极（例如，具有1000和10,000微米之间的器件宽度）。 大功率轨至轨电源nMOSFET的栅极由连接到相应电源轨的ESD检测电路的输出反相级控制。 在集成电路的正常工作期间，门被切换到公共地。

公开(公告)号：US07498860B2

公开(公告)日：2009-03-03

申请号：US11691590

申请日：2007-03-27

申请人： Dipankar Bhattacharya ,  Carol A. Huber ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Carol A. Huber ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03L5/00

CPC分类号： H03K19/017581 ,  H03K19/01759

摘要： A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.

摘要翻译： 作为提供给缓冲电路的第一控制信号的函数，缓冲器电路有选择地以至少第一模式和第二模式中的至少一个工作。 缓冲电路包括接口电路，其操作以接收参考第一电压电平的至少第二和第三控制信号，并产生参考第二电压电平的输出信号，第二电压电平大于第一电压电平。 输出信号是第一模式中的第二控制信号的函数，并且是第二模式中的第三控制信号的函数。 缓冲电路还包括耦合到接口电路的至少第一和第二电路部分，第一和第二电路部分中的每一个包括至少一个控制输入，其操作以接收由接口电路产生的输出信号。

公开(公告)号：US20090002017A1

公开(公告)日：2009-01-01

申请号：US11768496

申请日：2007-06-26

申请人： Dipankar Bhattacharya ,  Gregg R. Harleman ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Gregg R. Harleman ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03K19/0175 ,  H03K19/02

CPC分类号： H03K19/00376

摘要： A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.

摘要翻译： 以至少第一模式和第二模式之一工作的补偿缓冲器电路包括多个输出块和多个预驱动器，每个预驱动器具有连接到相应一个输出块的输入的输出。 输出块的各输出端连接在一起形成缓冲电路的输出。 输出块按顺序排列并且被二进制加权，使得给定的一个输出块的驱动强度大约是在给定输出块之前的输出块的驱动强度的两倍。 每个预驱动器根据提供给预驱动器的控制信号选择性地使连接到其上的相应输出块能够补偿用于缓冲电路可能经受的PVT变化的缓冲电路。 提供给预驱动器的各个控制信号共同表示二进制码字，第二模式中的二进制码字等价于第一模式中的二进制码字的算术移位。

公开(公告)号：US20080297226A1

公开(公告)日：2008-12-04

申请号：US11755955

申请日：2007-05-31

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Antonio M. Marques ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Antonio M. Marques ,  Bernard L. Morris

IPC分类号： G06G7/12

CPC分类号： H03K19/00384 ,  H04L5/16 ,  H04L25/0264

摘要： A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.

摘要翻译： 用于补偿至少第一MOS器件的输出阻抗的补偿电路，其中PVT变化对其可能经受的PVT变化包括：第一电流源，其产生具有基本恒定值的第一电流和产生第一MOS器件的第二电流源 第二电流具有可被编程为呈现给第二电流源的至少一个控制信号的函数的值。 比较器连接到第一和第二电流源的相应输出，并且可操作以测量第一和第二电流的相应值之间的差，并产生指示第一电流和第二电流的相对幅度的输出信号。 连接在比较器和第二电流源之间的反馈装置中的处理器接收比较器产生的输出信号，并产生用于根据输出信号控制第二电流的控制信号。 处理器可操作以控制第二电流的值，使得第二电流基本上等于第一电流。

公开(公告)号：US07391825B2

公开(公告)日：2008-06-24

申请号：US11046995

申请日：2005-01-31

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H04B10/06

CPC分类号： H03K5/2481 ,  H03K5/12

摘要： A comparator circuit having reduced pulse width distortion includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference between the first and second signals. An output stage is included in the comparator circuit for receiving the difference signal and for generating an output signal of the comparator circuit, the output signal being representative of the difference signal, the output stage having a switching point associated therewith. The comparator circuit further includes a voltage source coupled to the output of the differential amplifier. The voltage source is operative to generate a reference signal for establishing a common-mode voltage of the difference signal generated by the differential amplifier. The reference signal is substantially centered about the switching point of the output stage and substantially tracks the switching point over variations in process, voltage and/or temperature conditions to which the comparator circuit is subjected.

摘要翻译： 具有减小的脉冲宽度失真的比较器电路包括差分放大器，其操作以接收至少第一和第二信号并且放大第一和第二信号之间的差。 差分放大器在其输出处产生差分信号，其作为第一和第二信号之间的差异的函数。 输出级包括在比较器电路中，用于接收差分信号并产生比较器电路的输出信号，该输出信号代表差分信号，输出级具有与之相关的切换点。 比较器电路还包括耦合到差分放大器的输出的电压源。 电压源用于产生用于建立由差分放大器产生的差分信号的共模电压的参考信号。 参考信号基本上以输出级的切换点为中心，并且基本上跟踪比较器电路所经受的过程，电压和/或温度条件变化的切换点。

公开(公告)号：US07369489B1

公开(公告)日：2008-05-06

申请号：US10095800

申请日：2002-03-12

申请人： Dipankar Bhattacharya ,  Ketan A. Padwekar

发明人： Dipankar Bhattacharya ,  Ketan A. Padwekar

IPC分类号： H04L12/26 ,  H04J1/16 ,  G06F11/00 ,  G01R31/08

CPC分类号： H04L47/10 ,  H04L47/20 ,  H04L47/215 ,  H04L47/2458 ,  H04L47/31 ,  H04L47/32

摘要： The present invention defines a method of unbiased policing of data flow in a network device. According to an embodiment of the present invention, the token bucket policer of the network device ‘permits’ (forwards) incoming packets even when the size of the token bucket is less than the size of the incoming packets. Permitting incoming packets that are larger than the token bucket ensures that incoming packets are not dropped because of the size of the incoming packets. Incoming packets are policed by TBP when the magnitude comparison of the token bucket and a predetermined constant value does not comply with the policing scheme defined for the incoming packets. When a packet is ‘permitted’ (forwarded), the size of the token bucket is reduced by an amount equal to the size of the packet.

摘要翻译： 本发明定义了网络设备中数据流的无偏向性监管的方法。 根据本发明的实施例，即使当令牌桶的大小小于输入分组的大小时，网络设备的令牌桶监管器也允许（转发）传入的分组。 允许大于令牌桶的传入数据包确保传入数据包不会因为传入数据包的大小而被丢弃。 当令牌桶的大小比较和预定的常数值不符合为传入分组定义的监管方案时，TBP对进入的分组进行管理。 当数据包被“允许”（转发）时，令牌桶的大小减小等于数据包大小的数量。

公开(公告)号：US20070176635A1

公开(公告)日：2007-08-02

申请号：US11342175

申请日：2006-01-27

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Bernard Morris ,  Joseph Simko

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Bernard Morris ,  Joseph Simko

IPC分类号： H03K19/0175

CPC分类号： H03K19/017509 ,  H03K3/356104

摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.

摘要翻译： 用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，该输入级包括至少一个具有第一阈值电压 相关联。 电压电平转换器电路还包括锁存电路，其操作以存储表示输入信号的逻辑状态的信号，所述锁存电路包括具有与其相关联的第二阈值电压的至少一个晶体管器件，所述第二阈值电压大于 第一阈值电压。 电压钳位电路连接在输入级和锁存电路之间。 电压钳位电路用于限制输入级两端的电压，输入级两端的电压幅度作为第一和第二电压源之间的电压差的函数被控制。