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    DRAM memory cell
    2.
    发明授权
    DRAM memory cell 失效
    DRAM存储单元

    公开(公告)号：US07368752B2

    公开(公告)日：2008-05-06

    申请号：US10839800

    申请日：2004-05-06

    Applicant: Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

    Inventor： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

    IPC: H01L27/108 ,  H01L29/12 ,  H01L31/112

    CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

    Abstract: A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

    Abstract translation: DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层 在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器， 所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。

    FinFet device and method of fabrication
    6.
    发明申请
    FinFet device and method of fabrication 有权
    FinFet设备和制造方法

    公开(公告)号：US20050014318A1

    公开(公告)日：2005-01-20

    申请号：US10765910

    申请日：2004-01-29

    Applicant: Dirk Manger

    Inventor： Dirk Manger

    IPC: H01L21/336 ,  H01L29/786

    CPC classification number: H01L29/7851 ,  H01L29/66795

    Abstract: A transistor fin of a fin field-effect transistor is arranged between two contact structures. A gate electrode encapsulating the transistor fin on three sides is caused to recede by means of a nonlithographic process from contact trenches, which define the contact structures, before the formation of the contact structures. A distance a between the gate electrode and the contact structures is not subject to any tolerances due to the overlay of two independent lithographic masks. For a given extent of the gate electrode along the transistor fin, it is possible to minimize a distance A between the contact structures and thereby significantly increase the packing density of a plurality of fin field-effect transistors on a substrate compared with conventional devices.

    Abstract translation: 翅片场效应晶体管的晶体管鳍片布置在两个接触结构之间。 在形成接触结构之前，通过非平版印刷工艺，从形成接触结构的接触沟槽中，将晶体管鳍片封装在三面上的栅电极被后退。 门电极和接触结构之间的距离a由于两个独立的光刻掩模的覆盖而不受任何公差的影响。 对于沿着晶体管鳍片的给定范围的栅电极，可以使接触结构之间的距离A最小化，从而与常规器件相比，显着增加了衬底上的多个鳍状场效应晶体管的堆积密度。

    Integrated semiconductor memory and fabrication method
    7.
    发明授权
    Integrated semiconductor memory and fabrication method 有权
    集成半导体存储器和制造方法

    公开(公告)号：US06750098B2

    公开(公告)日：2004-06-15

    申请号：US10619970

    申请日：2003-07-15

    Applicant: Till Schlösser ,  Dirk Manger

    Inventor： Till Schlösser ,  Dirk Manger

    IPC: H01L218242

    CPC classification number: H01L27/10864 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66666

    Abstract: In semiconductor memories having a surrounding gate configuration, webs, i.e. vertical rectangular pillars made of substrate material, are formed at the surface of a semiconductor substrate and are surrounded by the gate electrodes in a lower region. Conventionally, it is not possible for word lines to make contact with the gate electrodes in the lower region of the webs without at the same time electrically influencing substrate regions at a higher level in the webs or short-circuiting bit lines from their sidewalls, unless complicated methods requiring additional lithography steps are used. A method for the self-aligning, selective contact-connection of the peripheral gate electrodes is performed with the aid of an insulation layer having a smaller layer thickness than the peripheral gate electrodes.

    Abstract translation: 在具有围绕栅极结构的半导体存储器中，在半导体衬底的表面上形成由衬底材料制成的腹板，即垂直矩形柱，并且在下部区域中由栅电极包围。 通常，字线不可能与幅材的下部区域中的栅极电极接触，而不会同时在幅材或短路位线从其侧壁电位影响衬底区域的较高水平，除非 使用需要额外光刻步骤的复杂方法。 借助于具有比外围栅极电极更薄的层厚度的绝缘层来执行外围栅电极的自对准，选择性接触连接的方法。

    Method of fabricating a semiconductor device
    9.
    发明授权
    Method of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07825031B2

    公开(公告)日：2010-11-02

    申请号：US11855809

    申请日：2007-09-14

    Applicant: Dirk Manger ,  Rolf Weis ,  Christoph Noelscher

    Inventor： Dirk Manger ,  Rolf Weis ,  Christoph Noelscher

    IPC: H01L21/302

    CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816

    Abstract: The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step.

    Abstract translation: 本发明涉及一种制造集成电路的方法，包括提供至少一层的步骤; 执行第一注入步骤，其中在第一入射方向上将颗粒注入所述层中; 执行第二注入步骤，其中在与所述第一入射方向不同的第二入射方向上将颗粒注入所述层中; 执行去除步骤，其中根据由第一和第二植入步骤产生的局部植入剂量部分去除该层。

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