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1.
公开(公告)号:US08248842B2
公开(公告)日:2012-08-21
申请号:US12732990
申请日:2010-03-26
申请人: Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人: Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号: G11C11/00
CPC分类号: G11C13/0023 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.
摘要翻译: 一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件,其中半导体存储器件包括:存储单元阵列,其包括多个存储单元,其中存储单元的第一端子连接到 多个第一行的对应的第一行和存储单元的第二端连接到多条第二行的对应的第二行; 偏置电路,用于将所选择的第二行的第二行偏置为参考电压和未选择的第二行至第一电压; 以及本地字线地址解码器将对应于第一电压的参考电压或泵浦电压施加到偏置电路。
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2.
公开(公告)号:US20100246248A1
公开(公告)日:2010-09-30
申请号:US12732990
申请日:2010-03-26
申请人: BEAK-HYUNG CHO , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人: BEAK-HYUNG CHO , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
CPC分类号: G11C13/0023 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.
摘要翻译: 一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件,其中半导体存储器件包括:存储单元阵列,其包括多个存储单元,其中存储单元的第一端子连接到 多个第一行的对应的第一行和存储单元的第二端连接到多条第二行的对应的第二行; 偏置电路,用于将所选择的第二行的第二行偏置为参考电压和未选择的第二行至第一电压; 以及本地字线地址解码器将对应于第一电压的参考电压或泵浦电压施加到偏置电路。
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3.
公开(公告)号:US20080165575A1
公开(公告)日:2008-07-10
申请号:US11969326
申请日:2008-01-04
申请人: Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人: Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
CPC分类号: G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译: 一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件,其中半导体存储器件包括:存储单元阵列,其包括多个存储单元,其中存储单元的第一端子连接到 多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。
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4.
公开(公告)号:US07710767B2
公开(公告)日:2010-05-04
申请号:US11969326
申请日:2008-01-04
申请人: Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人: Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号: G11C11/00
CPC分类号: G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译: 一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件,其中半导体存储器件包括:存储单元阵列,其包括多个存储单元,其中存储单元的第一端子连接到 多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。
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