公开(公告)号：US20140050020A1

公开(公告)日：2014-02-20

申请号：US13931275

申请日：2013-06-28

申请人： Jae-Young LEE ,  Bong-Jin KANG ,  Jung-Hwa HWANG ,  Ki-Woong YEOM ,  Young-Kwan KIM ,  Dong-Hyun SHON

发明人： Jae-Young LEE ,  Bong-Jin KANG ,  Jung-Hwa HWANG ,  Ki-Woong YEOM ,  Young-Kwan KIM ,  Dong-Hyun SHON

IPC分类号： G11C11/16

CPC分类号： G11C11/1653 ,  G11C7/1054 ,  G11C7/1081 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： Provided is a semiconductor memory device including a column decoder, a plurality of sub-cell blocks, and a bit line selection circuit. The column decoder is configured to decode column addresses and drive column selection signals. Each of the sub-cell blocks includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the plurality of bit lines and the plurality of word lines. The bit line selection circuit includes a plurality of bit line connection controllers, and is configured to select one or more bit lines in response to the column selection signals. Each of the bit line connection controllers electrically couples a respective first bit line to corresponding first and second local input/output (I/O) lines in response to first and second column selection signals of the column selection signals, respectively.

摘要翻译： 提供了包括列解码器，多个子单元块和位线选择电路的半导体存储器件。 列解码器被配置为解码列地址并驱动列选择信号。 每个子单元块包括多个位线，多个字线和连接到多个位线和多个字线的多个存储单元。 位线选择电路包括多个位线连接控制器，并且被配置为响应于列选择信号选择一个或多个位线。 每个位线连接控制器分别响应于列选择信号的第一和第二列选择信号将相应的第一位线电耦合到相应的第一和第二本地输入/输出（I / O）线。