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公开(公告)号：US07441131B2
公开(公告)日：2008-10-21
申请号：US11240923
申请日：2005-09-30
申请人： Douglas F. Pastorello , Douglas Holberg , William Gene Durbin , Biranchinath Sahu , Golam R. Chowdhury
发明人： Douglas F. Pastorello , Douglas Holberg , William Gene Durbin , Biranchinath Sahu , Golam R. Chowdhury
CPC分类号： G06F1/3203 , H03K19/0016
摘要： A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.
摘要翻译： 微控制器单元包括用于产生第一控制信号以开始微控制器单元的昏迷模式的处理器。 响应于第一控制信号的控制逻辑在第一电平产生使能信号，并且控制逻辑还响应于第二控制信号，以在第二电平产生使能信号。 电压调节器从输入电压产生调节电压。 电压调节器关闭，以响应于在第一电平的使能信号提供零伏调节电压，并且上电以响应于在第二电平的使能信号提供处于工作电平的调节电压。
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公开(公告)号：US20080091992A1
公开(公告)日：2008-04-17
申请号：US11531832
申请日：2006-09-14
IPC分类号： G01R31/28
CPC分类号： G01R31/31713 , G01R1/0408 , G01R31/31701 , G01R31/318544
摘要： A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input level. The technique substantially reduces or eliminates false detections of the test mode and substantially reduces or eliminates falsely enabling other (e.g., functional) mode(s) of the integrated circuit.
摘要翻译： 用于增加集成电路的终端的功能而不增加集成电路的终端数量的技术利用至少一个三电平终端和转换器电路，其提供指示集成电路的测试模式的逻辑电平，以响应于 相应的输入电平。 该技术基本上减少或消除了测试模式的错误检测，并且基本上减少或消除了错误地启用集成电路的其他（例如，功能）模式。
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公开(公告)号：US06557051B1
公开(公告)日：2003-04-29
申请号：US09484129
申请日：2000-01-15
IPC分类号： G06F1314
CPC分类号： G06F13/4291
摘要： A serial interface or port is configured so that: a Read command and a Write command can be performed substantially simultaneously; a shortened Read command, followed by another Read command, can be performed in reduced time, due to the shortening of the first Read command; and a continuous stream of Read commands can be performed consecutively with no time delay By performing Read and Write commands simultaneously on associated channels at a serial interface, the time required for such performance is reduced by as much as 50 percent.
摘要翻译： 串行接口或端口被配置为：可以基本上同时执行读命令和写命令; 由于缩短了第一个Read命令，缩短的Read命令后跟另一个Read命令可以在缩短的时间内执行; 并且可以连续执行连续的Read命令流，无需时间延迟通过在串行接口的相关通道上同时执行读写命令，这种性能所需的时间可减少多达50％。
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4.发明申请公开(公告)号：US20080246526A1
公开(公告)日：2008-10-09
申请号：US12120015
申请日：2008-05-13
IPC分类号： H03K3/02
CPC分类号： H03K3/0375 , H03K3/356147 , H03K19/0008
摘要： The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.
摘要翻译： 本发明包括一个微控制器单元，其包括用于产生掉电信号的处理器。 控制逻辑响应于掉电信号产生保持信号。 电压调节器响应于输入电压提供调节电压，并响应于掉电信号而断电。 响应于稳压器进入断电状态，由调节电压供电的至少一个数字设备进入断电模式。 所述至少一个数字设备提供提供给输入/输出单元的至少一个数字输出信号。 输入/输出单元也被连接以接收保持信号。 当至少一个数字设备进入掉电状态时，输入/输出单元响应于保持信号维持数字输出信号的最后状态。
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公开(公告)号：US07405601B2
公开(公告)日：2008-07-29
申请号：US11680026
申请日：2007-02-28
IPC分类号： H03K21/00
CPC分类号： H03K23/66 , H03K21/10 , H03L7/0805 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/193 , H03L7/1974 , H03L7/1976
摘要： In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.
摘要翻译： 在本发明的至少一个实施例中，一种用于将具有第一频率的第一信号除以分频比以产生较低频率信号的方法包括产生具有共同频率，第一脉冲宽度和不同相位的第一多个信号 。 第一组多个信号至少部分地基于具有第二脉冲宽度的至少一个信号。 至少部分地基于分频比，从多个脉冲宽度中选择第一脉冲宽度。 该方法包括顺序选择第一多个信号中的各个脉冲作为选择电路的输出信号，以产生具有低于第一频率的频率的输出信号。
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公开(公告)号：US06487674B1
公开(公告)日：2002-11-26
申请号：US09521675
申请日：2000-03-08
IPC分类号： G06F104
摘要： A data clock pin SCLK may be used to receive an SCLK signal as well as sleep and reset signals. During normal operation, the SCLK input pin may receive the SCLK signal, a square wave type clock signal. However, the SCLK signal may also be coupled to a one-shot within the device. When signal SCLK is held high for a predetermined period of time, the one-shot is triggered and a SLEEP signal is generated. The device reacts to this SLEEP signal by entering a sleep mode. Similarly, if the SCLK signal is held low for a predetermined period of time, the one-shot may output a low level RESET signal. This RESET signal resets the device into an initial condition state. Other modes of operation, such as test modes and the like may be entered into by holding the SCLK signal high or low in conjunction with a predetermined logic level on another pin (e.g., VREF).
摘要翻译： 数据时钟引脚SCLK可用于接收SCLK信号以及睡眠和复位信号。 在正常工作期间，SCLK输入引脚可以接收SCLK信号，即方波型时钟信号。 然而，SCLK信号也可以耦合到设备内的单触发。 当信号SCLK保持高电平达预定时间时，触发单触发，并产生SLEEP信号。 该设备通过进入睡眠模式对此SLEEP信号做出反应。 类似地，如果SCLK信号在预定时间段内保持低电平，则单稳态可以输出低电平复位信号。 该RESET信号将器件复位为初始状态。 通过将SCLK信号与另一个引脚（例如，VREF）上的预定逻辑电平相结合保持高或低可以输入其他操作模式，例如测试模式等。
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公开(公告)号：US06377198B1
公开(公告)日：2002-04-23
申请号：US09596156
申请日：2000-03-20
IPC分类号： H03M300
CPC分类号： H03K17/6872 , H03K17/693
摘要： The present invention provides a method and apparatus to define and sustain such a physical level by connecting the output through a transmission gate to an input pin. For a certain state of the output, one level of an input may be fed through to the output to generate an output voltage level. In the preferred embodiment of the present invention, a chip select signal {overscore (CS)} is used to define a low level logic signal. An control logic selectively switches a high level logic signal voltage (e.g., V+supply voltage) or the low level logic signal voltage ({overscore (CS)}) to produce an output digital logic signal. In a further embodiment of the present invention, separate logic level signals INH and INL may be selectively switched by control logic to generate an output logic level signal independent of supply voltages V+ and V−.
摘要翻译： 本发明提供了一种通过将输出通过传输门连接到输入引脚来定义和维持这种物理水平的方法和装置。 对于输出的某一状态，可以将一个输入电平馈送到输出以产生输出电压电平。 在本发明的优选实施例中，使用芯片选择信号{overscore（CS）}来定义低电平逻辑信号。 控制逻辑选择性地切换高电平逻辑信号电压（例如，V +电源电压）或低电平逻辑信号电压（{overscore（CS）}）以产生输出数字逻辑信号。 在本发明的另一个实施例中，分离的逻辑电平信号INH和INL可以被控制逻辑选择性地切换以产生独立于电源电压V +和V-的输出逻辑电平信号。
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8.发明授权Digital phase compensation methods and systems for a dual-channel analog-to-digital converter 有权用于双通道模数转换器的数字相位补偿方法和系统公开(公告)号：US06373415B1
公开(公告)日：2002-04-16
申请号：US09484480
申请日：2000-01-18
IPC分类号： H03M106
CPC分类号： G06J1/00
摘要： Phase compensation in a dual-channel analog-to-digital converter (ADC) is accomplished by holding conversion results in programmable length registers for controllable time periods. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing, is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay mechanism. A differential delay equal to &Dgr;I-&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value. The ADC according to the present invention further oversamples received analog signal at clock rates much higher than the output rate of the ADC, and delays are generated in the downstream filters connected to the ADC's.
摘要翻译： 双通道模数转换器（ADC）中的相位补偿通过将可编程长度寄存器中的转换结果保持在可控时间段内来实现。 双通道ADC包括第一和第二Δ-Σ调制器和数字滤波器，受到多个采样率的优化，用于优化延迟的粗调和微调。 在采样数据域中执行能量计算，该采样数据域是使用在数字域中执行的延迟补偿方案中的数字乘法技术来实现的。 进行滤波处理的数字数据被延迟预定量。 双通道ADC具有可编程通道延迟机制。 校正和补偿等于DELTAI-DELTAV的差分延迟，受制于正确能量值的可接受时间延迟。 根据本发明的ADC进一步以接收到的ADC的输出速率的时钟速率对接收到的模拟信号进行过采样，并且在连接到ADC的下行滤波器中产生延迟。
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9.发明授权Delay correction system and method for a voltage channel in a sampled data measurement system 有权采样数据测量系统中电压通道的延迟校正系统和方法公开(公告)号：US06304202B1
公开(公告)日：2001-10-16
申请号：US09484866
申请日：2000-01-18
IPC分类号： H03M100
CPC分类号： G06J1/00
摘要： Delay correction in a dual-channel analog-to-digital converter (ADC) is accomplished by insertion of coarse and fine delay correction registers prior to and after a frequency reduction element in a voltage channel. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay adjustment in the voltage channel thereof. A delay differential equal to &Dgr;I−&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value. The ADC according to the present invention further oversamples received analog signal at clock rates much higher than the output rate of the ADC, and delays are generated in the downstream filters connected to the ADCs.
摘要翻译： 在双通道模数转换器（ADC）中的延迟校正通过在电压通道中的频率降低元件之前和之后插入粗略和精细的延迟校正寄存器来实现。 双通道ADC包括第一和第二Δ-Σ调制器和数字滤波器，受到多个采样率的优化，用于优化延迟的粗调和微调。 在采样数据域中执行能量计算，该采样数据域是使用在数字域中执行的延迟补偿方案中的数字乘法技术来实现的。 进行滤波处理的数字数据被延迟预定量。 双通道ADC在其电压通道中提供可编程通道延迟调整。 等于DELTAI-DELTAV的延迟差分经过可靠的时间延迟进行校准和补偿，以产生正确的能量值。 根据本发明的ADC进一步以比ADC的输出速率高得多的时钟速率对接收到的模拟信号进行过采样，并且在连接到ADC的下游滤波器中产生延迟。
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公开(公告)号：US08020010B2
公开(公告)日：2011-09-13
申请号：US12144803
申请日：2008-06-24
CPC分类号： G06F1/3203 , G06F1/12 , G06F1/3225 , G06F1/3275 , G11C5/14 , G11C17/146 , G11C17/18 , Y02D10/14
摘要： A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock.
摘要翻译： 存储器功率控制器包括用于响应于源时钟产生第一时钟信号和第二时钟信号的时钟产生电路以及源时钟具有大于预定值的周期的确定。 响应于源时钟具有大于预定值的周期的确定产生第一时钟，并且响应于源时钟具有小于预定值的周期的确定而产生第二时钟。 存储器超时电路产生存储器使能/禁止信号，以响应于时钟信号来控制相关存储器的操作，以及确定源时钟具有大于预定值的周期。 存储器超时电路进一步使存储器使能/禁止信号与源时钟同步。
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