公开(公告)号：US06903979B1

公开(公告)日：2005-06-07

申请号：US10664758

申请日：2003-09-17

Applicant: Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter J. Hopper ,  Douglas J. Brisbin

Inventor： Yuri Mirgorodski ,  Vladislav Vashchenko ,  Peter J. Hopper ,  Douglas J. Brisbin

IPC: G11C16/00 ,  G11C16/10

CPC classification number: G11C16/10

Abstract: A method of programming a PMOS stacked gate memory cell is provided that utilizes the correlation between injection current and substrate current during the programming cycle to provide a feedback correction to the control gate of the memory cell to compensate for the negative potential shift on the floating gate as a result of its charging time.

Abstract translation: 提供了一种编程PMOS堆叠栅极存储单元的方法，其利用在编程周期期间的注入电流和衬底电流之间的相关性来向存储器单元的控制栅极提供反馈校正，以补偿浮置栅极上的负电位移位 作为其充电时间的结果。