公开(公告)号：US07359242B2

公开(公告)日：2008-04-15

申请号：US11180505

申请日：2005-07-12

申请人： Du-Yeul Kim

发明人： Du-Yeul Kim

IPC分类号： G11C11/34

CPC分类号： G11C29/802

摘要： In an embodiment, a semiconductor memory device has a small number of repair signal transmission lines. The semiconductor memory device includes m repair redundancy blocks, each including n repair redundant word lines, and m and n being natural numbers; and a control circuit generating n repair information signals to select the n repair redundant word lines and m block selection information signals to select the m repair redundancy blocks, and transmitting the n repair information signals and the m block selection information signals to the m repair redundancy blocks. The n repair information signals are shared by the m repair redundancy blocks. The control circuit includes n×m unit fuse boxes, n unit fuse boxes of which corresponding to each of the m repair redundancy blocks.

摘要翻译： 在一个实施例中，半导体存储器件具有少量的修复信号传输线。 半导体存储器件包括m个修复冗余块，每个修复冗余块包括n个修复冗余字线，m和n是自然数; 以及控制电路，生成n个修复信息信号，以选择n个修复冗余字线和m个块选择信息信号，以选择m个修复冗余块，并将n个修复信息信号和m个块选择信息信号发送到m个修复冗余 块。 n个维修信息信号由m个维修冗余块共享。 控制电路包括n×m个单元保险丝盒，n个单元保险丝盒，其对应于每个m个维修冗余块。

公开(公告)号：US20060198214A1

公开(公告)日：2006-09-07

申请号：US11342955

申请日：2006-01-30

申请人： Du-Yeul Kim ,  Sung-Min Seo ,  Byung-Hoon Jeong

发明人： Du-Yeul Kim ,  Sung-Min Seo ,  Byung-Hoon Jeong

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C5/063 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

摘要： A circuit for controlling timing skew in a semiconductor memory device includes a skew control circuit that is configured generate separate skew control signals for each respective one of a plurality of memory banks included in the semiconductor memory device. Related methods are also disclosed.

摘要翻译： 一种用于控制半导体存储器件中的定时偏移的电路包括一个偏斜控制电路，该偏斜控制电路配置为包括在半导体存储器件中的多个存储器体中的每个相应的一个产生单独的偏斜控制信号。 还公开了相关方法。

公开(公告)号：US20060126419A1

公开(公告)日：2006-06-15

申请号：US11302606

申请日：2005-12-14

申请人： Sang-Pyo Hong ,  Du-Yeul Kim

发明人： Sang-Pyo Hong ,  Du-Yeul Kim

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.

摘要翻译： 配置存储单元阵列块的方法包括将第一单元逻辑块划分为子阵列块并将子阵列块的一部分分配给第二单位逻辑块，其中存储单元阵列块对应于 子阵列块和第二单元逻辑块，并且子阵列块的部分和第二单元逻辑块共享外围电路。 第一单元逻辑块可以基于字线的单位和/或位线的单位被划分为子阵列块。 外围电路可以包括行解码器，列解码器，读出放大器和/或均衡/预充电电路。 还提供了相关寻址方法，存储单元阵列块和半导体存储器件。

公开(公告)号：US20060013049A1

公开(公告)日：2006-01-19

申请号：US11180505

申请日：2005-07-12

申请人： Du-Yeul Kim

发明人： Du-Yeul Kim

IPC分类号： G11C29/00

CPC分类号： G11C29/802

摘要： In an embodiment, a semiconductor memory device has a small number of repair signal transmission lines. The semiconductor memory device includes m repair redundancy blocks, each including n repair redundant word lines, and m and n being natural numbers; and a control circuit generating n repair information signals to select the n repair redundant word lines and m block selection information signals to select the m repair redundancy blocks, and transmitting the n repair information signals and the m block selection information signals to the m repair redundancy blocks. The n repair information signals are shared by the m repair redundancy blocks. The control circuit includes n×m unit fuse boxes, n unit fuse boxes of which corresponding to each of the m repair redundancy blocks.

摘要翻译： 在一个实施例中，半导体存储器件具有少量的修复信号传输线。 半导体存储器件包括m个修复冗余块，每个修复冗余块包括n个修复冗余字线，m和n是自然数; 以及控制电路，产生n个修复信息信号，以选择n个修复冗余字线和m个块选择信息信号，以选择m个修复冗余块，并将n个修复信息信号和m个块选择信息信号发送到m个修复冗余 块。 n个维修信息信号由m个维修冗余块共享。 控制电路包括n×m个单元保险丝盒，n个单元保险丝盒，其对应于每个m个维修冗余块。

公开(公告)号：US07580294B2

公开(公告)日：2009-08-25

申请号：US11702093

申请日：2007-02-05

申请人： Du-yeul Kim ,  Won-il Bae ,  Yong-gyu Chu ,  Jun-hyung Kim

发明人： Du-yeul Kim ,  Won-il Bae ,  Yong-gyu Chu ,  Jun-hyung Kim

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1048 ,  G11C2207/105

摘要： A semiconductor memory device includes a first row of pads including a first plurality of data input/output (I/O) pads; a second row of pads including a second plurality of data I/O pads; and a first I/O multiplexer associated with the first row of pads and providing first output data only to at least one data I/O pad of the first row of pads, even after a data I/O mode of the semiconductor memory device has changed. The semiconductor memory device also includes a second I/O multiplexer associated with the second row of pads and providing second output data only to at least one data I/O pad of the second row of pads, even after the data I/O mode has changed.

摘要翻译： 半导体存储器件包括：第一排焊盘，其包括第一多个数据输入/输出（I / O）焊盘; 包括第二多个数据I / O焊盘的第二排焊盘; 以及与第一排焊盘相关联的第一I / O多路复用器，并且即使在半导体存储器件的数据I / O模式具有第一I / O复用器之后，也仅将第一输出数据提供给第一排焊盘的至少一个数据I / O焊盘 改变了 半导体存储器件还包括与第二排焊盘相关联的第二I / O多路复用器，并且即使在数据I / O模式具有数据I / O模式之后，也仅向第二排焊盘的至少一个数据I / O焊盘提供第二输出数据 改变了

公开(公告)号：US20070189083A1

公开(公告)日：2007-08-16

申请号：US11702093

申请日：2007-02-05

申请人： Du-yeul Kim ,  Won-il Bae ,  Yong-gyu Chu ,  Jun-hyung Kim

发明人： Du-yeul Kim ,  Won-il Bae ,  Yong-gyu Chu ,  Jun-hyung Kim

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1048 ,  G11C2207/105

摘要： Embodiments of the invention provide a semiconductor memory device. In one embodiment, the invention provides a semiconductor memory device comprising a first row of pads comprising a first plurality of data input/output pads; a second row of pads comprising a second plurality of data input/output pads; and a first input/output multiplexer associated with the first row of pads and adapted to provide first output data only to at least one data input/output pad of the first row of pads, even after a data input/output mode of the semiconductor memory device has changed. The semiconductor memory device further comprises a second input/output multiplexer associated with the second row of pads and adapted to provide second output data only to at least one data input/output pad of the second row of pads, even after the data input/output mode has changed.

摘要翻译： 本发明的实施例提供一种半导体存储器件。 在一个实施例中，本发明提供一种半导体存储器件，其包括第一排焊盘，其包括第一多个数据输入/输出焊盘; 包括第二多个数据输入/输出焊盘的第二排焊盘; 以及与第一排焊盘相关联并且适于仅将第一输出数据提供给第一排焊盘的至少一个数据输入/输出焊盘的第一输入/输出多路复用器，即使在半导体存储器的数据输入/输出模式 设备已更改。 半导体存储器件还包括与第二排焊盘相关联的第二输入/输出多路复用器，并且适于仅将第二输出数据提供给第二排焊盘的至少一个数据输入/输出焊盘，即使在数据输入/输出 模式已经改变。

公开(公告)号：US20070030743A1

公开(公告)日：2007-02-08

申请号：US11500262

申请日：2006-08-07

申请人： Du-Yeul Kim ,  Byung-Chul Kim

发明人： Du-Yeul Kim ,  Byung-Chul Kim

IPC分类号： G11C29/00

CPC分类号： G11C29/808 ,  G11C29/785

摘要： A semiconductor memory device includes a memory cell array a redundant enable signal generating circuit and redundant decoder. The memory cell array includes memory cell array blocks including column selecting signal lines and lower and upper blocks. The redundant enable signal generating circuit programming defective addresses, during a mode setting operation and generating a redundant enable signal when the defective addresses are applied during an operation. The redundant decoder including decoders selecting a corresponding redundant column selecting signal line in response to the redundant enable signal, a corresponding block address, and a lower and upper block address, wherein each of the of decoders is electrically connected to one of the lower and upper blocks.

摘要翻译： 半导体存储器件包括存储单元阵列冗余使能信号发生电路和冗余解码器。 存储单元阵列包括包括列选择信号线和下块和上块的存储单元阵列块。 冗余使能信号发生电路在模式设置操作期间对缺陷地址进行编程，并且在操作期间应用缺陷地址时产生冗余使能信号。 所述冗余解码器包括响应于所述冗余使能信号，对应块地址以及下部和上部块地址来选择对应的冗余列选择信号线的解码器，其中每个解码器电连接到下部和上部 块。

公开(公告)号：US20060250162A1

公开(公告)日：2006-11-09

申请号：US11379200

申请日：2006-04-18

申请人： Du-Yeul Kim ,  Jun-Hyung Kim ,  Tai-Young Ko ,  Sang-Bo Lee

发明人： Du-Yeul Kim ,  Jun-Hyung Kim ,  Tai-Young Ko ,  Sang-Bo Lee

IPC分类号： H03F3/45

CPC分类号： G11C7/1072 ,  G11C7/1051 ,  G11C7/1069

摘要： A signal amplification circuit for a semiconductor memory device includes a current sense amplifier configured to receive a first signal pair and generate a second signal pair on a first pair of lines, an equalizer configured to equalize the first pair of lines, and a latch amplifier configured to generate a latch data output on a second pair of lines in response to the second signal pair.

摘要翻译： 一种用于半导体存储器件的信号放大电路包括：电流检测放大器，被配置为接收第一信号对并在第一对线路上产生第二信号对，配置成对第一对线路进行均衡的均衡器和配置成 以响应于第二信号对在第二对线路上产生锁存数据输出。

公开(公告)号：US07359264B2

公开(公告)日：2008-04-15

申请号：US11500262

申请日：2006-08-07

申请人： Du-Yeul Kim ,  Byung-Chul Kim

发明人： Du-Yeul Kim ,  Byung-Chul Kim

IPC分类号： G11C7/00

CPC分类号： G11C29/808 ,  G11C29/785

摘要： A semiconductor memory device includes a memory cell array a redundant enable signal generating circuit and redundant decoder. The memory cell array includes memory cell array blocks including column selecting signal lines and lower and upper blocks. The redundant enable signal generating circuit programming defective addresses, during a mode setting operation and generating a redundant enable signal when the defective addresses are applied during an operation. The redundant decoder including decoders selecting a corresponding redundant column selecting signal line in response to the redundant enable signal, a corresponding block address, and a lower and upper block address, wherein each of the of decoders is electrically connected to one of the lower and upper blocks.

摘要翻译： 半导体存储器件包括存储单元阵列冗余使能信号发生电路和冗余解码器。 存储单元阵列包括包括列选择信号线和下块和上块的存储单元阵列块。 冗余使能信号发生电路在模式设置操作期间对缺陷地址进行编程，并且在操作期间应用缺陷地址时产生冗余使能信号。 所述冗余解码器包括响应于所述冗余使能信号，对应块地址以及下部和上部块地址来选择对应的冗余列选择信号线的解码器，其中每个解码器电连接到下部和上部 块。

公开(公告)号：US07227807B2

公开(公告)日：2007-06-05

申请号：US11302606

申请日：2005-12-14

申请人： Sang-Pyo Hong ,  Du-Yeul Kim

发明人： Sang-Pyo Hong ,  Du-Yeul Kim

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.

摘要翻译： 配置存储单元阵列块的方法包括将第一单元逻辑块划分为子阵列块并将子阵列块的一部分分配给第二单位逻辑块，其中存储单元阵列块对应于 子阵列块和第二单元逻辑块，并且子阵列块的部分和第二单元逻辑块共享外围电路。 第一单元逻辑块可以基于字线的单位和/或位线的单位被划分为子阵列块。 外围电路可以包括行解码器，列解码器，读出放大器和/或均衡/预充电电路。 还提供了相关寻址方法，存储单元阵列块和半导体存储器件。