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    Method and an apparatus to sense supply voltage
    3.
    发明授权
    Method and an apparatus to sense supply voltage 有权
    检测电源电压的方法和装置

    公开(公告)号：US07449966B2

    公开(公告)日：2008-11-11

    申请号：US11431256

    申请日：2006-05-09

    申请人： Edward A. Burton ,  Robert J. Greiner ,  Anant S. Deval ,  Douglas R. Huard

    发明人： Edward A. Burton ,  Robert J. Greiner ,  Anant S. Deval ,  Douglas R. Huard

    IPC分类号： H03B27/00

    CPC分类号： H03K3/0315 ,  G01R19/0084 ,  H03K5/19

    摘要： A method and an apparatus to sense supply voltage have been disclosed. In one embodiment, the apparatus includes a resistor having a first end and a second end, the first end coupled to a voltage supply and a ring oscillator sensor coupled between the second end of the resistor and ground, the ring oscillator sensor having an output coupled to a computational element. Other embodiments have been claimed and described.

    摘要翻译： 已经公开了一种感测电源电压的方法和装置。 在一个实施例中，该装置包括具有第一端和第二端的电阻器，第一端耦合到电压源和耦合在电阻器的第二端和地之间的环形振荡器传感器，环形振荡器传感器具有输出耦合 到计算元素。 已经要求和描述了其它实施例。

    Apparatus and method to control self-timed and synchronous systems
    4.
    发明授权
    Apparatus and method to control self-timed and synchronous systems 有权
    控制自定时和同步系统的装置和方法

    公开(公告)号：US07282975B2

    公开(公告)日：2007-10-16

    申请号：US10750320

    申请日：2003-12-31

    申请人： Edward A. Burton ,  Paul Madland

    发明人： Edward A. Burton ,  Paul Madland

    IPC分类号： H03L7/00

    CPC分类号： G06F1/04

    摘要： An apparatus includes a substrate, a target timing circuit, a leakage timing circuit, and a control unit. The target timing circuit and the leakage timing circuits are formed on the substrate. The target timing circuit has a target timing circuit frequency related to a target frequency. The leakage timing circuit has a leakage timing circuit frequency related to a leakage current. The control unit maintains a substantially constant ratio between the target timing circuit frequency and the leakage timing circuit frequency. A method includes generating a first signal related to a target circuit frequency, generating a second signal related to a leakage current, and adjusting a control signal applied to a substrate to maintain a substantially constant frequency ratio between a first signal and the second signal.

    摘要翻译： 一种装置包括基板，目标定时电路，泄漏定时电路和控制单元。 目标定时电路和泄漏定时电路形成在基板上。 目标定时电路具有与目标频率相关的目标定时电路频率。 泄漏定时电路具有与漏电流相关的泄漏定时电路频率。 控制单元在目标定时电路频率和泄漏定时电路频率之间保持基本恒定的比率。 一种方法包括产生与目标电路频率相关的第一信号，产生与漏电流相关的第二信号，以及调整施加到衬底的控制信号，以保持第一信号和第二信号之间基本恒定的频率比。

    Addition of metal layers with signal reallocation to a microprocessor for increased frequency and lower power
    5.
    发明授权
    Addition of metal layers with signal reallocation to a microprocessor for increased frequency and lower power 有权
    添加具有信号重新分配到微处理器的金属层，以提高频率和更低的功率

    公开(公告)号：US07138716B2

    公开(公告)日：2006-11-21

    申请号：US10607550

    申请日：2003-06-27

    申请人： Edward A. Burton ,  Kumar Anshumali

    发明人： Edward A. Burton ,  Kumar Anshumali

    IPC分类号： H01L23/48 ,  H01L29/739

    CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and method of adding metal layers in a semiconductor device with signal reallocation are disclosed. The device has a first layer with a plurality of signal wires. A second layer adjacent to the first layer is also included that has a plurality of signal wires. The signal wires in the first and second layers are substantially parallel with each other. The signal wires are distributed between the first and second layer in a manner that reduces the wire capacitance and/or resistance thereby permitting higher frequency operation and lower power consumption in the device.

    摘要翻译： 公开了一种在具有信号再分配的半导体器件中添加金属层的半导体器件和方法。 该装置具有带有多条信号线的第一层。 还包括与第一层相邻的第二层，其具有多条信号线。 第一层和第二层中的信号线基本上彼此平行。 信号线以降低线电容和/或电阻的方式分布在第一和第二层之间，从而允许器件中的较高频率操作和较低功耗。

    Integrated circuit device with user-programmable conditional power-down means
    9.
    发明授权
    Integrated circuit device with user-programmable conditional power-down means 失效
    具有用户可编程条件断电功能的集成电路器件

    公开(公告)号：US5329178A

    公开(公告)日：1994-07-12

    申请号：US799499

    申请日：1991-11-27

    申请人： Edward A. Burton

    发明人： Edward A. Burton

    IPC分类号： H02J1/00 ,  H03K19/00 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/0016

    摘要： An integrated circuit device is provided with user-programmable power-down means for disabling a particular circuit in the device under control of a user-specified state of an input signal supplied to the device. In particular, for PLDs a power-down feature of this kind is simple to implement, requiring no additional I/O pins on the device, considerably reduces power consumption and renders the device more versatile than prior art devices.

    摘要翻译： 集成电路装置具有用户可编程的掉电装置，用于在被提供给装置的输入信号的用户指定状态的控制下禁用装置中的特定电路。 特别地，对于PLD，这种掉电功能易于实现，不需要设备上的额外I / O引脚，大大降低了功耗，并使器件比现有技术的器件更加通用。

    Circuit suitable for differential multiplexers and logic gates utilizing bipolar and field-effect transistors
    10.
    发明授权
    Circuit suitable for differential multiplexers and logic gates utilizing bipolar and field-effect transistors 失效
    电路适用于采用双极型和场效应晶体管的差分复用器和逻辑门

    公开(公告)号：US5155387A

    公开(公告)日：1992-10-13

    申请号：US727811

    申请日：1991-07-08

    申请人： Thomas D. Fletcher ,  Edward A. Burton

    发明人： Thomas D. Fletcher ,  Edward A. Burton

    IPC分类号： G06F7/50 ,  G06F7/503 ,  H03K17/693 ,  H03K19/0944 ,  H03K19/21

    CPC分类号： G06F7/503 ,  H03K17/693 ,  H03K19/09448 ,  H03K19/21

    摘要： A circuit employable as a differential multiplexer (10, 310, or 610) or as a differential logic gate (110, 210, 250, 410, or 510) of either the OR/NOR or EXCLUSIVE OR/EXCLUSIVE NOR type contains four pass gates that operate on four circuit input signals and are controlled by two additional circuit input signals. Two of the pass gates drive a bipolar transistor serially coupled to a first FET driven from the other two pass gates. Likewise, the second pair of pass gates drive another bipolar transistor serially coupled to another FET driven from the first pair of pass gates. The bipolar transistors supply respective circuit output signals. The two FETs are of a first polarity. The circuit preferably includes a pair of FETs of a second polarity opposite to the first polarity. The second pair of FETs are arranged so as to provide output pull-up/pull-down assistance for the bipolar transistors.

    摘要翻译： OR / NOR或EXCLUSIVE OR / EXCLUSIVE NOR类型的可用作差分多路复用器（10,310或610）或差分逻辑门（110,210,250,410或510）的电路包含四通道 其操作在四个电路输入信号上，并由两个额外的电路输入信号控制。 两个通路驱动双极晶体管串联耦合到从另外两个通过栅极驱动的第一FET。 类似地，第二对通孔驱动另一双极晶体管串联耦合到从第一对通孔驱动的另一个FET。 双极晶体管提供相应的电路输出信号。 两个FET是第一极性。 电路优选地包括与第一极性相反的第二极性的一对FET。 第二对FET被布置成为双极晶体管提供输出上拉/下拉辅助。