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    METHOD OF OPERATING A MEMORY SYSTEM HAVING AN ERASE CONTROL UNIT
    2.
    发明申请
    METHOD OF OPERATING A MEMORY SYSTEM HAVING AN ERASE CONTROL UNIT 有权
    操作具有擦除控制单元的存储器系统的方法

    公开(公告)号：US20160093387A1

    公开(公告)日：2016-03-31

    申请号：US14827930

    申请日：2015-08-17

    申请人： Eun Chu Oh ,  Hong Rak Son ,  Junjin Kong

    发明人： Eun Chu Oh ,  Hong Rak Son ,  Junjin Kong

    IPC分类号： G11C16/16 ,  G11C16/34 ,  G11C16/26

    CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/26 ,  G11C16/3468

    摘要： A method of operating a memory system including a nonvolatile memory including a memory block, and a memory controller including an erase control unit, includes performing pre-reading a plurality of memory cells connected to a selected word line of the memory block, generating an off cell count based on the pre-reading result, by operation of the erase control unit, comparing the off cell count with a reference value to generate a comparison result, and changing an erase operation condition based on the comparison result, by operation of the nonvolatile memory, and erasing the memory block according to the changed erase operation condition.

    摘要翻译： 一种操作包括包括存储器块的非易失性存储器的存储器系统的方法和包括擦除控制单元的存储器控​​制器，包括执行预读取连接到所述存储器块的选定字线的多个存储器单元，产生关断 基于预读取结果的单元计数，通过擦除控制单元的操作，将关闭单元计数与参考值进行比较以产生比较结果，以及通过非易失性存储器的操作来改变基于比较结果的擦除操作条件 存储器，并根据改变的擦除操作条件擦除存储器块。

    NONVOLATILE MEMORY DEVICE AND DATA WRITE METHOD
    5.
    发明申请
    NONVOLATILE MEMORY DEVICE AND DATA WRITE METHOD 有权
    非易失性存储器件和数据写入方法

    公开(公告)号：US20140281824A1

    公开(公告)日：2014-09-18

    申请号：US14179614

    申请日：2014-02-13

    申请人： EUN CHU OH ,  JUNJIN KONG ,  YOUNGGEON YOO ,  KIJUN LEE

    发明人： EUN CHU OH ,  JUNJIN KONG ,  YOUNGGEON YOO ,  KIJUN LEE

    IPC分类号： G06F11/16 ,  G11C11/16

    CPC分类号： G11C11/1675 ,  G11C7/1006 ,  G11C11/2275 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2029/0411

    摘要： A data write method of a nonvolatile memory device is provided which includes receiving write data to be stored in selected memory cells; reading data stored in the selected memory cells; processing the write data according to a plurality of data modulation manners to generate a plurality of modulated data values; calculating the number of flip bits and the number of switching bits when the write data and the plurality of modulated data values are overwritten on the selected memory cells, each flip bit indicating that a logical value of a selected memory cell is reversed and each switching bit indicating that a logical value of a selected memory cell is switched from a first logical value to a second logical value; and selecting one of the write data and the plurality of modulated data values according to calculating the number of flip bits and the number of switching bits.

    摘要翻译： 提供了一种非易失性存储器件的数据写入方法，包括接收要存储在所选存储器单元中的写数据; 读取存储在所选存储单元中的数据; 根据多个数据调制方式处理写入数据以产生多个调制数据值; 当选择的存储单元写入写入数据和多个调制数据值时，计算翻转位数和切换位数，每个翻转位指示所选存储单元的逻辑值相反，并且每个开关位 指示所选存储单元的逻辑值从第一逻辑值切换到第二逻辑值; 以及根据计算翻转位数和切换位数来选择写入数据和多个调制数据值之一。

    MEMORY SYSTEM WITH INTERLEAVED ADDRESSING METHOD
    6.
    发明申请
    MEMORY SYSTEM WITH INTERLEAVED ADDRESSING METHOD 审中-公开
    具有异步寻址方法的记忆系统

    公开(公告)号：US20120246395A1

    公开(公告)日：2012-09-27

    申请号：US13426259

    申请日：2012-03-21

    申请人： Kyoung Lae Cho ,  Hong Rak Son ,  Eun Chu Oh

    发明人： Kyoung Lae Cho ,  Hong Rak Son ,  Eun Chu Oh

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G06F12/0638

    摘要： Disclosed is a memory system which includes a nonvolatile memory device including a memory cell array having a plurality of word lines including a first set of word lines storing first data having a high bit error rate, and a second set of word lines storing second data having low bit error rate less than the high bit error rate, and a memory controller that during a program operation maps logical addresses for a portion of the first data and a portion of the second data onto a selected word line selected from the plurality of word lines.

    摘要翻译： 公开了一种包括非易失性存储器件的存储器系统，该非易失性存储器件包括具有多个字线的存储单元阵列，该多个字线包括存储具有高误码率的第一数据的第一组字线和存储具有第二数据的第二数据的第二组， 低位错误率低于高位误码率;以及存储器控制器，其在编程操作期间将用于所述第一数据的一部分和所述第二数据的一部分的逻辑地址映射到从所述多个字线中选择的所选字线上 。