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    METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE 有权
    无平面化和相关半导体器件制造被动元件的方法

    公开(公告)号：US20080054393A1

    公开(公告)日：2008-03-06

    申请号：US11928798

    申请日：2007-10-30

    Applicant: Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

    Inventor： Anil Chinthakindi ,  Timothy Dalton ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Anthony Stamper ,  Kunal Vaed

    IPC: H01L29/00 ,  H01L21/02

    CPC classification number: H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

    Abstract translation: 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT
    3.
    发明申请
    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT 有权
    集成薄膜电阻与直接接触

    公开(公告)号：US20070290272A1

    公开(公告)日：2007-12-20

    申请号：US11846595

    申请日：2007-08-29

    Applicant: Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    Inventor： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    IPC: H01L29/00

    CPC classification number: H01L27/016

    Abstract: A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

    Abstract translation: 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

    INTEGRATED PARALLEL PLATE CAPACITORS
    4.
    发明申请
    INTEGRATED PARALLEL PLATE CAPACITORS 有权
    集成并联板电容器

    公开(公告)号：US20070190760A1

    公开(公告)日：2007-08-16

    申请号：US11275544

    申请日：2006-01-13

    Applicant: Douglas Coolbaugh ,  Hanyi Ding ,  Ebenezer Eshun ,  Michael Gordon ,  Zhong-Xiang He ,  Anthony Stamper

    Inventor： Douglas Coolbaugh ,  Hanyi Ding ,  Ebenezer Eshun ,  Michael Gordon ,  Zhong-Xiang He ,  Anthony Stamper

    IPC: H01L21/425

    CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.

    Abstract translation: 形成在集成电路的后端的平行电容器采用与后端（具有相同材料，厚度等）的该级别上的其它互连件同时形成的导电电容器板。 使用与后端（优选双镶嵌）级别上的其它互连件相同的工艺将电容器板设置在层间电介质中。 一些版本的电容器在板中具有穿孔，并且垂直导电构件连接相同极性的所有板，从而与实心板相比增加了可靠性，节省了空间并增加了电容密度。

    HI-K DIELECTRIC LAYER DEPOSITION METHODS
    6.
    发明申请
    HI-K DIELECTRIC LAYER DEPOSITION METHODS 失效
    HI-K介电层沉积方法

    公开(公告)号：US20060270247A1

    公开(公告)日：2006-11-30

    申请号：US10908789

    申请日：2005-05-26

    Applicant: Douglas Coolbaugh ,  Ebenezer Eshun ,  Kenneth Stein ,  Kunal Vaed

    Inventor： Douglas Coolbaugh ,  Ebenezer Eshun ,  Kenneth Stein ,  Kunal Vaed

    IPC: H01L21/336

    CPC classification number: H01L21/02181 ,  C23C16/405 ,  C23C16/45523 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/28194 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517

    Abstract: Methods of forming a high dielectric constant dielectric layer are disclosed including providing a process chamber including a holder for supporting a substrate, introducing a first gas comprising a high dielectric constant (Hi-K) dielectric precursor and an oxygen (O2) oxidant into the process chamber to form a first portion of the high dielectric constant dielectric layer on the substrate, and switching from a flow of the first gas to a flow of a second gas comprising the Hi-K dielectric precursor and an ozone (O3) oxidant to form a second portion of the high dielectric constant dielectric layer on the first portion. In an alternative embodiment, another portion can be formed on the second portion using the oxygen oxidant. The invention increases throughput by at least 20% without reliability or leakage degradation and without the need for additional equipment.

    Abstract translation: 公开了形成高介电常数电介质层的方法，包括提供包括用于支撑衬底的保持器的处理室，引入包含高介电常数（Hi-K）电介质前体和氧（O 2） / SUB>）氧化剂进入处理室以形成衬底上的高介电常数电介质层的第一部分，并且从第一气体的流动切换到包括Hi-K电介质前体的第二气体的流动，以及 臭氧（O 3 3）氧化剂以形成第一部分上的高介电常数介电层的第二部分。 在替代实施例中，可以使用氧氧化剂在第二部分上形成另一部分。 本发明将产量提高了至少20％，而没有可靠性或泄漏降级，并且不需要额外的设备。

    High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature
    7.
    发明申请
    High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature 有权
    高容差TCR平衡型高电流电阻，用于射频CMOS和射频SiGe BiCMOS应用以及基于分级的分级参数化电池设计套件，具有可调TCR和ESD电阻镇流功能

    公开(公告)号：US20050221572A1

    公开(公告)日：2005-10-06

    申请号：US11124247

    申请日：2005-05-06

    Applicant: Ebenezer Eshun ,  Steven Voldman

    Inventor： Ebenezer Eshun ,  Steven Voldman

    IPC: H01C7/06 ,  H01L21/02 ,  H01L21/20 ,  H01L23/62 ,  H01L27/02 ,  H01L27/08 ,  H01L29/00

    CPC classification number: H01C7/06 ,  H01L27/0288 ,  H01L27/0802 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor. A computer aided design tool with graphical and schematic features is provided to enable generation of hierarchical parameterized cells for a resistor element with the ability to provide customization, personalization and tunability of TCR, TCR matching, and high current and ESD robustness.

    Abstract translation: 因此，电阻器件结构及其制造方法，其中电阻器件结构发明包括多个交替导电膜和绝缘膜层，至少两个导电膜层并联电连接以提供通过电阻器的高电流 器件在高频下具有升高的温度和机械稳定性。 交替导电膜和绝缘膜层可以是平面或非平面的几何空间取向。 交替导电膜和绝缘膜层可以包括横向和垂直部分，其被设计成能够通过物理电阻器内的自镇流效应在结构本身内实现均匀的电流密度流动。 提供了具有图形和原理图功能的计算机辅助设计工具，以便能够为电阻元件生成分层参数化单元，具有提供TCR，TCR匹配以及高电流和ESD鲁棒性的定制，个性化和可调性的能力。

    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT
    8.
    发明申请
    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT 失效
    集成薄膜电阻与直接接触

    公开(公告)号：US20070166909A1

    公开(公告)日：2007-07-19

    申请号：US11275611

    申请日：2006-01-19

    Applicant: Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    Inventor： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    IPC: H01L21/8244

    CPC classification number: H01L27/016

    Abstract: A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. *Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

    Abstract translation: 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

    INTEGRATION SCHEME FOR HIGH GAIN FET IN STANDARD CMOS PROCESS
    9.
    发明申请
    INTEGRATION SCHEME FOR HIGH GAIN FET IN STANDARD CMOS PROCESS 审中-公开
    标准CMOS工艺中高增益FET的集成方案

    公开(公告)号：US20070099386A1

    公开(公告)日：2007-05-03

    申请号：US11163791

    申请日：2005-10-31

    Applicant: Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  James Slinkman ,  Michael Zierak

    Inventor： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  James Slinkman ,  Michael Zierak

    IPC: H01L21/336 ,  H01L29/788

    CPC classification number: H01L29/66659 ,  H01L21/26586

    Abstract: A method for fabricating high gain FETs that substantially reduces or eliminates unwanted variation in device characteristics caused by using a prior art shadow masking process is provided. The inventive method employs a blocking mask that at least partially extends over the gate region wherein after extension and halo implants an FET having an asymmetric halo region asymmetric extension regions or a combination thereof is fabricated. The inventive method thus provides high gain FETs in which the variation of device characteristics is substantially reduced. The present invention also relates to the resulting asymmetric high gain FET device that is fabricated utilizing the method of the present invention.

    Abstract translation: 提供了一种制造高增益FET的方法，其基本上减少或消除了由使用现有技术的阴影掩蔽处理引起的器件特性的不必要的变化。 本发明的方法采用阻挡掩模，其在栅极区域上至少部分地延伸，其中在延伸和卤素注入之后，制造具有不对称卤素区域不对称延伸区域或其组合的FET。 因此，本发明的方法提供了高增益FET，其中器件特性的变化显着降低。 本发明还涉及利用本发明的方法制造的非对称高增益FET器件。

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