公开(公告)号：US07704876B2

公开(公告)日：2010-04-27

申请号：US11847657

申请日：2007-08-30

申请人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：US20080020546A1

公开(公告)日：2008-01-24

申请号：US11862706

申请日：2007-09-27

申请人： Edward COONEY ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

发明人： Edward COONEY ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

IPC分类号： H01L21/475 ,  H01L21/302 ,  H01L21/32 ,  H01L21/467

CPC分类号： H01L21/76829 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/78

摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

摘要翻译： 本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。 可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。 粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。 可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。 用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。 然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。

公开(公告)号：US20080020230A1

公开(公告)日：2008-01-24

申请号：US11865215

申请日：2007-10-01

申请人： Daniel Edelstein ,  Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Daniel Edelstein ,  Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： B32B15/00 ,  B05D1/36

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/12493 ,  H01L2924/00

摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

摘要翻译： 通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性 通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。 通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。

公开(公告)号：US20070275565A1

公开(公告)日：2007-11-29

申请号：US11838942

申请日：2007-08-15

申请人： Edward Cooney ,  Robert Geffken ,  Vincent McGahay ,  William Motsiff ,  Mark Murray ,  Amanda Piper ,  Anthony Stamper ,  David Thomas ,  Elizabeth Webster

发明人： Edward Cooney ,  Robert Geffken ,  Vincent McGahay ,  William Motsiff ,  Mark Murray ,  Amanda Piper ,  Anthony Stamper ,  David Thomas ,  Elizabeth Webster

IPC分类号： H01L21/311

CPC分类号： H01L23/53238 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76838 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for semiconductor structure includes a plurality of adjacent wiring levels, conductors within each of the wiring levels, and liners at least partially surrounding each of the conductors. The liners of adjacent wiring levels are made of different materials which have different etching characteristics and are selectively etchable with respect to one another. The liners can be tantalum, tungsten, etc. The liners surround at least three sides of the conductors. Each of the wiring levels has a first insulator layer which has a first dielectric material. The liners and the conductors are positioned within the first dielectric material. A second insulator layer has a second dielectric material over the first insulator layer. The first dielectric material has a lower dielectric constant than the second dielectric material. The first dielectric material can be silicon dioxide, fluorinated silicon dioxide (FSD), microporous glasses, etc. The second dielectric material can be one of nitrides, oxides, tantalum, tungsten, etc.

摘要翻译： 用于半导体结构的方法和结构包括多个相邻布线层，每个布线层内的导体和至少部分地围绕每个导体的衬垫。 相邻布线层的衬垫由具有不同蚀刻特性并且可相对于彼此选择性地蚀刻的不同材料制成。 衬垫可以是钽，钨等。衬里围绕导体的至少三个侧面。 每个布线层具有第一绝缘体层，其具有第一介电材料。 衬垫和导体位于第一介电材料内。 第二绝缘体层在第一绝缘体层上具有第二电介质材料。 第一电介质材料具有比第二电介质材料低的介电常数。 第一介电材料可以是二氧化硅，氟化二氧化硅（FSD），微孔玻璃等。第二介电材料可以是氮化物，氧化物，钽，钨等中的一种。

公开(公告)号：US07300867B2

公开(公告)日：2007-11-27

申请号：US11174985

申请日：2005-07-05

申请人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：US20070155164A1

公开(公告)日：2007-07-05

申请号：US11687017

申请日：2007-03-16

申请人： Steven Barkyoumb ,  Jonathan Chapple-Sokol ,  Edward Cooney ,  Keith Downes ,  Thomas McDevitt ,  William Murphy

发明人： Steven Barkyoumb ,  Jonathan Chapple-Sokol ,  Edward Cooney ,  Keith Downes ,  Thomas McDevitt ,  William Murphy

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76873

摘要： A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.

摘要翻译： 一种用于在半导体结构的制造过程中减少铜籽晶层的腐蚀的方法和结构。 在结构（或包含结构的晶片）离开溅射工具的真空环境之前，将结构加热到高于溅射工具外部环境的水冷凝温度的温度。 结果，当结构离开溅射工具时，水蒸气不会在结构上冷凝，因此防止了水蒸气对种子层的腐蚀。 或者，在结构离开溅射工具环境之前，可以在籽晶层的顶部形成耐水蒸汽的保护层。 在另一替代实施例中，种子层可以包括铜合金（例如用铝），其在暴露于水蒸汽时生长出耐水蒸气的保护层。

公开(公告)号：US20060027929A1

公开(公告)日：2006-02-09

申请号：US11247818

申请日：2005-10-11

申请人： Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Stephen Luce ,  Thomas McDevitt ,  Lee Nicholson ,  Anthony Stamper

发明人： Edward Cooney ,  John Fitzsimmons ,  Jeffrey Gambino ,  Stephen Luce ,  Thomas McDevitt ,  Lee Nicholson ,  Anthony Stamper

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/58

CPC分类号： H01L21/76831 ,  H01L21/02107 ,  H01L21/02203 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76868

摘要： Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed-pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant Into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.

公开(公告)号：US06958540B2

公开(公告)日：2005-10-25

申请号：US10604026

申请日：2003-06-23

申请人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/768 ,  H01L23/42 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures are disclosed for forming dual damascene back-end-of-line (BEOL) structure using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）结构的互连结构，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：US20050146040A1

公开(公告)日：2005-07-07

申请号：US11053706

申请日：2005-02-08

申请人： Edward Cooney ,  Robert Geffken ,  Anthony Stamper

发明人： Edward Cooney ,  Robert Geffken ,  Anthony Stamper

IPC分类号： H01L21/768 ,  H01L21/4763 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76865

摘要： A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.

公开(公告)号：US06426822B1

公开(公告)日：2002-07-30

申请号：US09104916

申请日：1998-06-25

申请人： Gary Edwin Winter ,  Thomas Edward Cooney

发明人： Gary Edwin Winter ,  Thomas Edward Cooney

IPC分类号： H04B1004

CPC分类号： H04B10/505 ,  H04B10/50575

摘要： A pilot signal is generated and injected into the input (108) of a signal modulator (104). The harmonic signal of a pilot signal produced at the output (110) and due to the non-linear transfer function of the signal modulator (104) is coherently sampled in the time domain to produce a plurality of digital samples. The digital samples are averaged to produce an average harmonic signal value. The bias voltage at which the signal modulator (104) is biased is adjusted to minimize the magnitude of the average harmonic signal value.

摘要翻译： 产生导频信号并将其注入信号调制器（104）的输入端（108）。 在输出端（110）产生的导频信号的谐波信号和由信号调制器（104）的非线性传递函数产生的谐波信号在时域被相干采样以产生多个数字样本。 数字样本被平均以产生平均谐波信号值。 调整信号调制器（104）被偏置的偏置电压以最小化平均谐波信号值的大小。