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    Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit
    1.
    发明授权
    Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit 有权
    集成电路加热器，用于减少集成电路材料中的应力和集成电路的芯片引线，并优化集成电路器件的性能

    公开(公告)号：US09318409B1

    公开(公告)日：2016-04-19

    申请号：US14496870

    申请日：2014-09-25

    Applicant: Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    Inventor： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC: H01L21/66 ,  H01L23/34

    CPC classification number: H01L25/065 ,  G01K7/00 ,  G01K7/427 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.

    Abstract translation: 一种包括第一检测器的装置，包括输出，设置在集成电路芯片的第一位置并且被配置为确定第一温度信息，芯片加热器，包括用于接收控制信号的输入端，所述芯片加热器设置在所述第一温度信息的第二位置处 集成电路并且被配置为基于所述控制信号加热包括所述第一位置和所述第二位置的所述集成电路装置的区域;以及加热器控制器，包括耦合到所述第一检测器的输出的第一输入以接收所述第一温度 信息和耦合到芯片加热器的输入的输出，加热器控制器被配置为基于第一温度信息生成控制信号。

    INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT
    2.
    发明申请
    INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT 有权
    用于集成电路集成电路材料和芯片引线的集成电路加热器，并优化集成电路器件的性能

    公开(公告)号：US20160093549A1

    公开(公告)日：2016-03-31

    申请号：US14496870

    申请日：2014-09-25

    Applicant: Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    Inventor： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC: H01L23/34

    CPC classification number: H01L25/065 ,  G01K7/00 ,  G01K7/427 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.

    Abstract translation: 一种包括第一检测器的装置，包括输出，设置在集成电路芯片的第一位置并且被配置为确定第一温度信息，芯片加热器，包括用于接收控制信号的输入端，所述芯片加热器设置在所述第一温度信息的第二位置处 集成电路并且被配置为基于所述控制信号加热包括所述第一位置和所述第二位置的所述集成电路装置的区域;以及加热器控制器，包括耦合到所述第一检测器的输出的第一输入以接收所述第一温度 信息和耦合到芯片加热器的输入的输出，加热器控制器被配置为基于第一温度信息生成控制信号。

    Electronic device including a capacitor and a process of forming the same
    3.
    发明授权
    Electronic device including a capacitor and a process of forming the same 有权
    包括电容器的电子器件及其形成方法

    公开(公告)号：US09064785B2

    公开(公告)日：2015-06-23

    申请号：US11780900

    申请日：2007-07-20

    Applicant: Bradley P. Smith ,  Edward O. Travis

    Inventor： Bradley P. Smith ,  Edward O. Travis

    IPC: G02F1/1333 ,  G02F1/1343 ,  H01L21/66 ,  H01L49/02

    CPC classification number: H01L22/20 ,  H01L22/12 ,  H01L28/40

    Abstract: An electronic device can include electronic components and an insulating layer overlying the electronic components. The electronic device can also include a capacitor overlying the insulating layer, wherein the capacitor includes a first electrode and a second electrode. The second electrode can include an opening, wherein from a top view, a defect lies within the opening. In another aspect, a process of forming an electronic device can include forming a first capacitor electrode layer over a substrate, forming a dielectric layer over the first capacitor electrode layer, and forming a second capacitor electrode layer over the dielectric layer. The process can also include detecting a defect and removing a first portion of the second capacitor electrode layer corresponding to the defect, wherein a second portion of the second capacitor electrode layer remains over the dielectric layer.

    Abstract translation: 电子设备可以包括电子部件和覆盖电子部件的绝缘层。 电子器件还可以包括覆盖绝缘层的电容器，其中电容器包括第一电极和第二电极。 第二电极可以包括开口，其中从顶部看，缺陷位于开口内。 另一方面，形成电子器件的方法可以包括在衬底上形成第一电容器电极层，在第一电容器电极层上形成电介质层，并在电介质层上形成第二电容器电极层。 该过程还可以包括检测缺陷并去除对应于缺陷的第二电容器电极层的第一部分，其中第二电容器电极层的第二部分保留在电介质层上。

    Integrated Assist Features for Epitaxial Growth
    7.
    发明申请
    Integrated Assist Features for Epitaxial Growth 有权
    外延生长的综合辅助特征

    公开(公告)号：US20110269300A1

    公开(公告)日：2011-11-03

    申请号：US13182568

    申请日：2011-07-14

    Applicant: Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

    Inventor： Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

    IPC: H01L21/20 ,  G06F17/50

    CPC classification number: H01L21/02595 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639

    Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

    Abstract translation: 提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

    Integrated assist features for epitaxial growth
    8.
    发明授权
    Integrated assist features for epitaxial growth 有权
    用于外延生长的集成辅助功能

    公开(公告)号：US08003539B2

    公开(公告)日：2011-08-23

    申请号：US11650253

    申请日：2007-01-04

    Applicant: Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

    Inventor： Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

    IPC: H01L21/311

    CPC classification number: H01L21/02595 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639

    Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

    Abstract translation: 提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

    EPI T-gate structure for CoSi2 extendibility
    10.
    发明授权
    EPI T-gate structure for CoSi2 extendibility 有权
    EPI T-gate结构，CoSi2可扩展性

    公开(公告)号：US07622339B2

    公开(公告)日：2009-11-24

    申请号：US11340049

    申请日：2006-01-26

    Applicant: Mark D. Hall ,  Dharmesh Jawarani ,  Mehul D. Shroff ,  Edward O. Travis

    Inventor： Mark D. Hall ,  Dharmesh Jawarani ,  Mehul D. Shroff ,  Edward O. Travis

    IPC: H01L21/338

    CPC classification number: H01L21/28114 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

    Abstract translation: 半导体工艺和装置提供由多晶硅结构（10）和外延生长的多晶硅层（70）形成并且具有较窄的底部临界尺寸（例如，等于或低于40nm）形成的T形结构（96）和更大的 顶部临界尺寸（例如，在40nm以上），使得硅化物可以在至少T形结构（96）的上部区域（90）中由第一材料（例如CoSi 2）形成，而不会增加 在较小的临界尺寸下，某些硅化物可能会发生聚集和排空引起的电阻。

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