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公开(公告)号：US09043526B2
公开(公告)日：2015-05-26
申请号：US13528146
申请日：2012-06-20
IPC分类号： G06F13/40
CPC分类号： G06F13/4018 , G06F9/4411 , G06F13/423
摘要： Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.
摘要翻译： 每个PCIe设备可以包括支持多个不同通道配置的媒体访问控制（MAC）接口和物理（PHY）接口。 这些接口可以包括支持1×32,2×16,4×8,8×4,16×2和32×1通信的硬件模块。 代替使用专用迹线将MAC接口中的每个硬件模块物理连接到PHY接口中的相应硬件模块，该设备可以包括两个总线控制器，其仲裁哪些硬件模块连接到耦合两个接口的内部总线。 当需要不同的通道配置时，总线控制器将相应的硬件模块耦合到内部总线。 以这种方式，不同的通道配置与其他通道配置共享总线的相同通道（和线）。 因此，共享总线仅需要包括足够的通道（和电线），以适应最宽的通道配置。
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公开(公告)号：US20130346665A1
公开(公告)日：2013-12-26
申请号：US13528146
申请日：2012-06-20
IPC分类号： G06F13/20
CPC分类号： G06F13/4018 , G06F9/4411 , G06F13/423
摘要： Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.
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公开(公告)号：US08572455B2
公开(公告)日：2013-10-29
申请号：US12546095
申请日：2009-08-24
IPC分类号： H03M13/00
CPC分类号： G06F11/141 , G06F11/1008 , G06F11/1666
摘要： Systems and methods to respond to error detection are provided. First data may be received at a first memory controller port in response to a read command issued from the first memory controller port. The read command may be issued as a second read command from a second memory controller port after determining that the first data contains a first uncorrectable error. Second data may be received at the second memory controller port in response to the second read command. A repair write command may be issued from the first memory controller port after determining that the second data does not contain any errors. The repair write command may initiate writing the second data from the first memory controller port.
摘要翻译： 提供了响应错误检测的系统和方法。 响应于从第一存储器控制器端口发出的读取命令，可以在第一存储器控制器端口接收第一数据。 在确定第一数据包含第一不可校正错误之后，可以从第二存储器控制器端口发出读取命令作为第二读取命令。 响应于第二读取命令，可以在第二存储器控制器端口接收第二数据。 在确定第二数据不包含任何错误之后，可以从第一存储器控制器端口发出修复写入命令。 修复写入命令可以开始从第一存储器控制器端口写入第二数据。
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4.发明授权Memory controller for improved read port selection in a memory mirrored system 失效内存控制器，用于改善内存镜像系统中的读取端口选择公开(公告)号：US08127087B2
公开(公告)日：2012-02-28
申请号：US12369806
申请日：2009-02-12
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F9/3824 , G06F9/3855 , G06F11/141 , G06F11/1443 , G06F11/1666
摘要： Read commands on a mirrored memory computer system are scheduled by utilizing information about pending memory access requests. A conflict queue is configured to track a read/write queue associated with each of a plurality of memory ports on the mirrored memory system. The conflict queue determines a predicted latency on each memory port based on the contents of each of the read/write queues. A compare logic unit is coupled to the conflict queue, wherein the compare logic unit compares a predicted latency of a primary memory and a mirrored memory and schedules read commands to the memory port with the lowest predicted latency.
摘要翻译： 通过利用有关未决内存访问请求的信息来调度镜像内存计算机系统上的读命令。 冲突队列被配置为跟踪与镜像存储器系统上的多个存储器端口中的每一个相关联的读/写队列。 冲突队列基于每个读/写队列的内容来确定每个存储器端口上的预测等待时间。 比较逻辑单元耦合到冲突队列，其中比较逻辑单元比较主存储器和镜像存储器的预测等待时间，并以最低预测等待时间将读取命令调度到存储器端口。
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公开(公告)号：US20110066921A1
公开(公告)日：2011-03-17
申请号：US12561687
申请日：2009-09-17
CPC分类号： H04L1/1845 , G06F11/1443 , H04L2001/0092
摘要： Systems and methods to respond to error detection are provided. A particular method may include issuing a first command to a first redrive device and a second command to a second redrive device. The method may also include reissuing the second command to the second redrive device in response to detecting a transmission error between a memory controller and the second redrive device. The method may further include storing at a first buffer first data that is received from the first redrive device in response to the first command. The method may include storing at a second buffer second data that is received from the second redrive device in response to the reissued second command. The method also may include merging the second data with the first data.
摘要翻译： 提供了响应错误检测的系统和方法。 特定方法可以包括向第一重新启动设备发出第一命令，以及向第二重新启动设备发出第二命令。 响应于检测到存储器控制器和第二重新驱动设备之间的传输错误，该方法还可以包括将第二命令重新发送到第二重新启动设备。 该方法还可以包括在第一缓冲器处存储响应于第一命令从第一重新启动设备接收到的数据。 该方法可以包括在第二缓冲器中存储响应于重新发出的第二命令从第二重新启动设备接收的第二数据。 该方法还可以包括将第二数据与第一数据合并。
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公开(公告)号：US20110047440A1
公开(公告)日：2011-02-24
申请号：US12546095
申请日：2009-08-24
CPC分类号： G06F11/141 , G06F11/1008 , G06F11/1666
摘要： Systems and methods to respond to error detection are provided. First data may be received at a first memory controller port in response to a read command issued from the first memory controller port. The read command may be issued as a second read command from a second memory controller port after determining that the first data contains a first uncorrectable error. Second data may be received at the second memory controller port in response to the second read command. A repair write command may be issued from the first memory controller port after determining that the second data does not contain any errors. The repair write command may initiate writing the second data from the first memory controller port.
摘要翻译： 提供了响应错误检测的系统和方法。 响应于从第一存储器控制器端口发出的读取命令，可以在第一存储器控制器端口接收第一数据。 在确定第一数据包含第一不可校正错误之后，可以从第二存储器控制器端口发出读取命令作为第二读取命令。 响应于第二读取命令，可以在第二存储器控制器端口接收第二数据。 在确定第二数据不包含任何错误之后，可以从第一存储器控制器端口发出修复写入命令。 修复写入命令可以开始从第一存储器控制器端口写入第二数据。
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7.发明申请公开(公告)号：US20090132876A1
公开(公告)日：2009-05-21
申请号：US11942116
申请日：2007-11-19
IPC分类号： G11C29/00
CPC分类号： G06F11/106 , G11C5/04 , G11C29/42 , G11C29/44 , G11C29/56008 , G11C29/76 , G11C2029/0411 , G11C2029/1208 , G11C2029/5606
摘要： A method and apparatus to maintain memory read error information concurrently across multiple ranks in a computer memory. An error detection unit associates a read error with a particular rank and with a particular chip in the rank. The error detection unit reports the error and the associated rank ID and chip ID to an error logging unit. The error logging unit maintains, for each rank ID and chip ID for which an error has been detected, a total number of errors that occur. A memory controller uses a fault pattern in the error logging unit to replace failing memory chips or memory ranks with a spare memory chip or a spare memory rank.
摘要翻译： 一种在计算机存储器中跨多个级别同时维持存储器读取错误信息的方法和装置。 错误检测单元将读取错误与特定级别和排名中的特定芯片相关联。 错误检测单元向错误记录单元报告错误和相关的排名ID和芯片ID。 错误记录单元对于检测到错误的每个等级ID和芯片ID维护发生的错误总数。 存储器控制器使用错误记录单元中的故障模式来替换故障存储器芯片或具有备用存储器芯片或备用存储器等级的存储器级别。
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8.发明申请USING A PCI STANDARD HOT PLUG CONTROLLER TO MODIFY THE HIERARCHY OF A DISTRIBUTED SWITCH 有权使用PCI标准热插拔控制器来修改分布式开关的分层公开(公告)号：US20120311221A1
公开(公告)日：2012-12-06
申请号：US13528192
申请日：2012-06-20
IPC分类号： G06F13/20
CPC分类号： G06F13/4081 , G06F13/20
摘要： The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.
摘要翻译： 标准热插拔控制器（SHPC）规范可用于在分布式交换机中生成PCI消息，以断开和/或连接端点的虚拟层次与基于多根输入/输出虚拟化（MR-IOV）连接的主机 ）。 管理控制器可以指示SHPC生成指定特定虚拟层级以与特定主机断开连接的PCI分组。 连接到主机和SHPC的上行端口接收PCI分组，并使用标识分组中的虚拟端点的报头来索引到路由表中，以识别连接到端点的分布式交换机中的下游端口。 一旦PCI数据包穿过交换机并到达下游端口，下游端口会更改路由逻辑，逻辑上将主机与指定的虚拟层次结构断开连接。
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9.发明申请Transmitting Retry Request Associated With Non-Posted Command Via Response Credit Channel 失效通过响应信用信道发送与非发布命令相关的重试请求公开(公告)号：US20120011283A1
公开(公告)日：2012-01-12
申请号：US12834313
申请日：2010-07-12
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： In a particular embodiment, a method is disclosed that includes, at a first computing device coupled to a second computing device via a bus, receiving a request from the second computing device to complete a non-posted command, where the request is received via a request credit channel of the bus, and where the first computing device is configured to receive requests to complete non-posted commands and requests to complete posted commands via the request credit channel. The method also includes removing the request to complete the non-posted command from the request credit channel. The method further includes transmitting a retry request associated with the non-posted command to the second computing device via a response credit channel of the bus.
摘要翻译： 在特定实施例中，公开了一种方法，其包括在经由总线耦合到第二计算设备的第一计算设备处接收来自第二计算设备的请求以完成未发布的命令，其中通过经由 请求总线的信用信道，并且其中第一计算设备被配置为接收完成非发布的命令的请求以及通过请求信用信道完成发布的命令的请求。 该方法还包括从请求信用信道中移除完成非发布命令的请求。 该方法还包括经由总线的响应信用信道向第二计算设备发送与非发布命令相关联的重试请求。
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公开(公告)号：US08055813B2
公开(公告)日：2011-11-08
申请号：US12132711
申请日：2008-06-04
IPC分类号： G06F13/00 , G06F15/177
CPC分类号： G06F13/385
摘要： In a system for communicating data from a processor to a plurality of register groupings that includes a plurality of registers and a plurality of register decoding logic entities, each register is associated with one of the plurality of register groupings. The plurality of register decoding logic entities is arranged in a data communication ring and is assigned to a register grouping. Each register decoding logic entity is configured to: receive a data packet that includes a data unit intended for a set of the registers in communication with the register decoding logic entity; write the data unit to each of the set of registers; determine if the register decoding logic entity is set to a relay mode; and if the register decoding logic entity is set to the relay mode, then update the data packet to reflect an address corresponding to a next register decoding logic entity in the data communication ring and then transmit the data packet to the next register decoding logic entity for which the data packet is intended.
摘要翻译： 在用于将数据从处理器传送到包括多个寄存器和多个寄存器解码逻辑实体的多个寄存器组的系统中，每个寄存器与多个寄存器组中的一个相关联。 多个寄存器解码逻辑实体被布置在数据通信环中并被分配给寄存器分组。 每个寄存器解码逻辑实体被配置为：接收包括用于与寄存器解码逻辑实体通信的一组寄存器的数据单元的数据分组; 将数据单元写入每个寄存器组; 确定寄存器解码逻辑实体是否设置为中继模式; 并且如果寄存器解码逻辑实体被设置为中继模式，则更新数据分组以反映与数据通信环中的下一个寄存器解码逻辑实体对应的地址，然后将数据分组发送到下一个寄存器解码逻辑实体 数据包的意图。
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