公开(公告)号：US5916451A

公开(公告)日：1999-06-29

申请号：US450113

申请日：1995-05-25

申请人： Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon Jay Robbins ,  Madhavan Swaminathan ,  George Eugene White

发明人： Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon Jay Robbins ,  Madhavan Swaminathan ,  George Eugene White

IPC分类号： H01L23/538 ,  H05K1/03 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H01B13/00

CPC分类号： H05K1/116 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2924/15312 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/115 ,  H05K2201/0367 ,  H05K3/4007 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/467 ,  Y10S428/901 ,  Y10T428/24926

摘要： A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

公开(公告)号：US5757079A

公开(公告)日：1998-05-26

申请号：US577677

申请日：1995-12-21

申请人： Michael McAllister ,  James McDonald ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon J. Robbins ,  Madhavan Swaminathan ,  George Eugene White

发明人： Michael McAllister ,  James McDonald ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon J. Robbins ,  Madhavan Swaminathan ,  George Eugene White

IPC分类号： H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/22 ,  H05K3/46 ,  H01L23/48 ,  H01L23/52 ,  H01L23/58 ,  H01L29/40

CPC分类号： H01L23/5382 ,  H01L21/485 ,  H05K3/225 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K2203/162 ,  H05K3/0082 ,  H05K3/4644

摘要： A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

摘要翻译： 提供了一种具有定义的修补线的多层薄膜结构和用于修复多层薄膜结构（MLTF）中的互连和/或制造工程电荷（EC）的方法。 该方法包括使用光刻技术（例如直接写入曝光技术）来确定在与结构的顶部金属层相邻的薄膜层处的MLTF中的任何互连缺陷，以限定修复互连所需的顶面连接和/或使EC ，并使用添加剂或阴极金属化技术形成顶表面金属化和修补线。

公开(公告)号：US20120083114A1

公开(公告)日：2012-04-05

申请号：US12897826

申请日：2010-10-05

申请人： ERIC DANIEL PERFECTO ,  Harry David Cox ,  Timothy Harrison Daubenspeck ,  David L. Questad ,  Brian Richard Sundlof

发明人： ERIC DANIEL PERFECTO ,  Harry David Cox ,  Timothy Harrison Daubenspeck ,  David L. Questad ,  Brian Richard Sundlof

IPC分类号： H01L21/768

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00015 ,  H01L2924/01074 ,  H01L2924/06 ,  H01L2924/053 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method for reducing stress on under ball metallurgy (UBM) is disclosed. A collar is disposed around the ball to provide support, and prevent solder interaction in the undercut areas of the UBM. In one embodiment, the collar is comprised of photosensitive polyimide.

摘要翻译： 公开了一种减少球磨冶金（UBM）应力的方法。 围绕球设置套环以提供支撑，并且防止UBM的底切区域中的焊料相互作用。 在一个实施例中，套环由光敏聚酰亚胺组成。

公开(公告)号：US06998327B2

公开(公告)日：2006-02-14

申请号：US10299567

申请日：2002-11-19

申请人： Jeffrey B. Danielson ,  Balaram Ghosal ,  James Kuss ,  Matthew Wayne Oonk ,  Chandrika Prasad ,  Eric Daniel Perfecto ,  Roy Yu

发明人： Jeffrey B. Danielson ,  Balaram Ghosal ,  James Kuss ,  Matthew Wayne Oonk ,  Chandrika Prasad ,  Eric Daniel Perfecto ,  Roy Yu

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L21/768 ,  H01L2221/68359 ,  H01L2221/68363 ,  H05K3/002 ,  H05K3/007 ,  H05K3/4007 ,  H05K3/467 ,  H05K2201/0367 ,  H05K2203/016

摘要： A thin film transfer join process in which a multilevel thin film structure is formed on a carrier, the multilevel thin film structure is joined to a final substrate and then the carrier is removed. Once the carrier is removed, the dielectric material and metallic material that were once joined to the carrier are now exposed. The dielectric material is then etched back so that the exposed metallic material protrudes beyond the dielectric material. Also disclosed is a module made by the foregoing process.

摘要翻译： 在载体上形成多层薄膜结构的薄膜转移连接工艺，多层薄膜结构连接到最终的衬底，然后去除载体。 一旦移除了载体，就已经暴露出曾经接合到载体上的电介质材料和金属材料。 然后将电介质材料回蚀刻，使得暴露的金属材料突出超过电介质材料。 还公开了通过前述方法制成的模块。

公开(公告)号：US06448169B1

公开(公告)日：2002-09-10

申请号：US08576185

申请日：1995-12-21

申请人： William Brearley ,  Laertis Economikos ,  Paul F. Findeis ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Arthur Gilman Merryman ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  James Patrick Wood ,  Roy Yu

发明人： William Brearley ,  Laertis Economikos ,  Paul F. Findeis ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Arthur Gilman Merryman ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  James Patrick Wood ,  Roy Yu

IPC分类号： H01L2144

CPC分类号： B23K3/0607 ,  B23K2101/40 ,  H05K3/3484 ,  H05K2201/10734 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/043 ,  Y10T29/49204

摘要： An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.

摘要翻译： 一种用于制造半导体器件的装置包括具有多个IO引脚的输入输出（IO）面，并且位于与沉积器邻接的操作位置。 该装置包括将第一保持构件保持在第一位置; 保持半导体器件处于操作位置的第二保持构件。 存储器和半导体器件在操作位置协作以将焊球连接结构沉积到IO焊盘。 该装置还包括用于将存储器和半导体器件中的至少一个从操作位置移动到临时取向的分离构件。 临时方向建立了适于使焊球连接结构与沉积器脱离接触的存放器和半导体器件之间的间隔距离。

公开(公告)号：US06342407B1

公开(公告)日：2002-01-29

申请号：US09731619

申请日：2000-12-07

申请人： Lewis Sigmund Goldmann ,  Eric Daniel Perfecto ,  Raed A. Sherif ,  William Frederick Shutler ,  Hilton T. Toy

发明人： Lewis Sigmund Goldmann ,  Eric Daniel Perfecto ,  Raed A. Sherif ,  William Frederick Shutler ,  Hilton T. Toy

IPC分类号： H01L2144

CPC分类号： H01L23/10 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/16315 ,  H01L2224/0401

摘要： A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periphery of the carrier. There is an upper adhesion layer shaped as a matching an upper frame facing downwardly from the cover towards the lower frame. Above the soft lower frame is a lower metal adhesion layer. Between the upper frame and the lower adhesion layer is a solder layer which has been heated to seal the cover to the chip carrier. The soft frame can include a channel through which a metal to metal via-seal is formed by the lower metal adhesion layer and the solder through the channel through the soft layer or there can be a lateral extension of the lower metal adhesion layer to a distal location beyond the periphery of the soft lower frame.

摘要翻译： 密封电子电路模块包括具有顶表面的陶瓷芯片载体，具有配合表面的盖和在载体和盖之间的载体周边处的密封。 密封件包括位于载体周边的载体顶部的非金属软下框架，优选聚酰亚胺。 存在形成为与从顶盖向下朝向下框架向下的上框架匹配的上粘合层。 软下框架上方是下金属粘合层。 在上框架和下粘合层之间是焊接层，其被加热以将盖密封到芯片载体。 软框架可以包括通道，通过下金属粘合层和焊料通过通过软层的通道形成金属对金属的通孔密封件，或者可以将下金属粘合层的侧向延伸到远端 超出软下框架周边的位置。

公开(公告)号：US6149048A

公开(公告)日：2000-11-21

申请号：US057421

申请日：1998-04-08

申请人： William Brearley ,  Laertis Economikos ,  Paul F. Findeis ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Arthur Gilman Merryman ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  James Patrick Wood ,  Roy Yu

发明人： William Brearley ,  Laertis Economikos ,  Paul F. Findeis ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Arthur Gilman Merryman ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  James Patrick Wood ,  Roy Yu

IPC分类号： B23K3/06 ,  H05K3/34 ,  B23K1/00

CPC分类号： B23K3/0607 ,  H05K3/3484 ,  B23K2201/40 ,  H05K2201/10734 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/043 ,  Y10T29/49204

摘要： An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.

公开(公告)号：US20130249066A1

公开(公告)日：2013-09-26

申请号：US13427940

申请日：2012-03-23

申请人： CHARLES L. ARVIN ,  KENNETH BIRD ,  CHARLES C. GOLDSMITH ,  SUNG K. KANG ,  MINHUA LU ,  CLARE JOHANNA MCCARTHY ,  ERIC DANIEL PERFECTO ,  SRINIVASA S.N. REDDY ,  KRYSTYNA WALERIA SEMKOW ,  THOMAS ANTHONY WASSICK

发明人： CHARLES L. ARVIN ,  KENNETH BIRD ,  CHARLES C. GOLDSMITH ,  SUNG K. KANG ,  MINHUA LU ,  CLARE JOHANNA MCCARTHY ,  ERIC DANIEL PERFECTO ,  SRINIVASA S.N. REDDY ,  KRYSTYNA WALERIA SEMKOW ,  THOMAS ANTHONY WASSICK

IPC分类号： H01L23/495 ,  H01L21/28

CPC分类号： H01L21/7685 ,  H01L21/321 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/0382 ,  H01L2224/0401 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1111 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13562 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/181 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.

公开(公告)号：US06444919B1

公开(公告)日：2002-09-03

申请号：US08477054

申请日：1995-06-07

申请人： Laertis Economikos ,  Mukta Shaji Farooq ,  Michael Ford McAllister ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Madhavan Swaminathan ,  Thomas Anthony Wassick ,  George White

发明人： Laertis Economikos ,  Mukta Shaji Farooq ,  Michael Ford McAllister ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Madhavan Swaminathan ,  Thomas Anthony Wassick ,  George White

IPC分类号： H05K103

CPC分类号： H01L23/5382 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0286 ,  H05K1/0289 ,  H05K3/467 ,  H01L2924/00

摘要： A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.

摘要翻译： 基板上的薄膜布线方案。 薄膜布线方案包括在基板上的第一和第二芯片位置的每一个处的多个芯片连接焊盘，散布在第一和第二芯片位置中的每一个的芯片连接焊盘之间的多个定向布线，至少一个 所述定向布线与所述第一和第二芯片位置中的每一个处的所述其它方向布线中的至少一个正交;以及多个芯片布线，其将所述第一芯片位置处的方向布线与所述定向布线连接， 第二个芯片站点。

公开(公告)号：US5898222A

公开(公告)日：1999-04-27

申请号：US950262

申请日：1997-10-14

申请人： Mukta Shaji Farooq ,  Suryanarayana Kaja ,  Eric Daniel Perfecto ,  George Eugene White

发明人： Mukta Shaji Farooq ,  Suryanarayana Kaja ,  Eric Daniel Perfecto ,  George Eugene White

IPC分类号： H01L23/498 ,  H01L23/532 ,  H05K1/03 ,  H05K3/06 ,  H05K3/10 ,  H05K3/38 ,  H05K3/46 ,  H01L23/48

CPC分类号： H05K3/108 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2203/0597 ,  H05K2203/1105 ,  H05K3/062 ,  H05K3/388 ,  H05K3/4644

摘要： The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

摘要翻译： 本发明一般涉及一种用于封盖铜电互连的新结构和方法。 更具体地，本发明包括一种新颖的结构，其中半导体衬底内的一个或多个铜电互连被封盖以获得坚固的电互连结构。 还公开了一种用于获得这种封盖铜电互连结构的方法。 这些封装的互连可以是单层或多层结构。 类似地，被封装的互连结构本身可以由单层或多层材料组成。