公开(公告)号：US08635430B2

公开(公告)日：2014-01-21

申请号：US12821170

申请日：2010-06-23

申请人： David Craddock ,  Thomas A. Gregg ,  Dan F. Greiner ,  Eric N. Lais

发明人： David Craddock ,  Thomas A. Gregg ,  Dan F. Greiner ,  Eric N. Lais

IPC分类号： G06F12/00

CPC分类号： G06F12/10 ,  G06F9/355 ,  G06F12/0292 ,  G06F2212/206

摘要： An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

公开(公告)号：US20120203934A1

公开(公告)日：2012-08-09

申请号：US13447691

申请日：2012-04-16

申请人： ERIC N. LAIS ,  STEVE THURBER

发明人： ERIC N. LAIS ,  STEVE THURBER

IPC分类号： G06F3/00

CPC分类号： G06F13/404 ,  G06F13/28 ,  G06F13/36 ,  G06F2213/0058

摘要： A data processing system includes a processor core, a system memory including a first data structure including a plurality of entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers, and an input/output (I/O) subsystem including a plurality of PEs each having an associated PE number, where each of the plurality of PEs including one or more requesters each having a respective requester ID. An I/O host bridge, responsive to receiving an I/O message including a requester ID and an address, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index and validates the address by reference to the accessed entry in the second data structure. The I/O host bridge, responsive to successful validation, provides a service indicated by the I/O message.

摘要翻译： 数据处理系统包括处理器核心，系统存储器，其包括第一数据结构，所述第一数据结构包括将请求者标识符（ID）映射到可分割端点（PE）号码的多个条目，以及包括多个的输入/输出（I / O）子系统 的每个具有相关联的PE号的PE，其中所述多个PE中的每一个包括一个或多个请求者，每个请求者各自具有相应的请求者ID。 I / O主机桥响应于接收到包括请求者ID和地址的I / O消息，通过参考来自第一数据结构的第一条目来确定PE号码，并且响应于确定PE号码，访问第二个 利用PE号码作为索引输入第二数据结构，并通过参考第二数据结构中的访问条目来验证地址。 响应成功验证的I / O主机桥提供由I / O消息指示的服务。

公开(公告)号：US20120185632A1

公开(公告)日：2012-07-19

申请号：US13007800

申请日：2011-01-17

申请人： Eric N. Lais ,  Gregory M. Nordstrom ,  Steven M. Thurber

发明人： Eric N. Lais ,  Gregory M. Nordstrom ,  Steven M. Thurber

IPC分类号： G06F13/20

CPC分类号： G06F13/404

摘要： A method, system and computer program product are provided for implementing PCI-Express memory domains for single root virtualized devices. A PCI host bridge (PHB) includes a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) are used to associate MMIO domains with PCI memory VF BAR spaces. One MDD is provided for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to the PCI host bridge (PHB). The MDT used with the MDD includes having a number of entries limited to a predefined total number of SRIOV VFs to be configured. A VF BAR Stride, which may be further implemented as a VF BAR Stride Capability Structure, is provided to reduce the number of MDDs required to map SRIOV VF BAR spaces. A particular definition of the MDD is provided to reduce the number of MDDs required to at most one per SRIOV bus segment below a PHB.

摘要翻译： 提供了一种用于实现单根虚拟化设备的PCI-Express存储域的方法，系统和计算机程序产品。 PCI主机桥（PHB）包括内存映射IO（MMIO）域描述符（MDD），MMIO域表（MDT）用于将MMIO域与PCI内存VF BAR空间相关联。 为每个总线段的每个独特的VF BAR空间大小提供一个MDD，将单个根IO虚拟化（SRIOV）设备连接到PCI主机桥（PHB）。 与MDD一起使用的MDT包括许多条目限于要配置的预定义的SRIOV VF的总数。 提供可以进一步实现为VF BAR步幅能力结构的VF BAR Stride，以减少映射SRIOV VF BAR空间所需的MDD数量。 提供了MDD的特定定义，以减少PHB以下每个SRIOV总线段中每个至多一个MDD所需的MDD数量。

公开(公告)号：US20120036305A1

公开(公告)日：2012-02-09

申请号：US12849980

申请日：2010-08-04

申请人： ERIC N. LAIS ,  STEVE THURBER

发明人： ERIC N. LAIS ,  STEVE THURBER

IPC分类号： G06F13/20 ,  G06F13/36

CPC分类号： G06F9/45533 ,  G06F13/36 ,  G06F2009/45579

摘要： A data processing system includes a processor core, a system memory including a first data structure including entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers and a second data structure, and an input/output (I/O) subsystem including an I/O bridge and a plurality of PEs each including one or more requesters each having a respective requester ID. The I/O host bridge, responsive to receiving an I/O message including a requester ID, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index, where the second entry indicating one or more of the plurality of PEs affected by the message. The I/O host bridge services the I/O message with reference to each of the plurality of PEs indicated by the second entry.

摘要翻译： 数据处理系统包括处理器核心，系统存储器，其包括第一数据结构，该第一数据结构包括将请求者标识符（ID）映射到可分割端点（PE）号码和第二数据结构的条目，以及输入/输出（I / O） I / O桥和多个PE，每个PE包括一个或多个请求者，每个请求者具有相应的请求者ID。 所述I / O主机桥响应于接收到包括请求者ID的I / O消息，通过参考来自所述第一数据结构的第一条目来确定PE号码，并且响应于确定所述PE号码，访问所述PE号码的第二条目 利用PE号作为索引的第二数据结构，其中第二条目指示受该消息影响的多个PE中的一个或多个。 参考由第二条目指示的多个PE中的每一个，I / O主机桥服务I / O消息。

公开(公告)号：US20110320756A1

公开(公告)日：2011-12-29

申请号：US12821171

申请日：2010-06-23

申请人： David Craddock ,  Thomas A. Gregg ,  Dan F. Greiner ,  Eric N. Lais ,  Donald W. Schmidt

发明人： David Craddock ,  Thomas A. Gregg ,  Dan F. Greiner ,  Eric N. Lais ,  Donald W. Schmidt

IPC分类号： G06F12/10

CPC分类号： G06F13/28 ,  G06F12/1081

摘要： Various address translation formats are available for use in obtaining system memory addresses for use by requestors, such as adapter functions, in accessing system memory. The particular address translation format to be used by a given requestor is pre-registered in a device table entry associated with that requestor.

摘要翻译： 各种地址转换格式可用于获取系统内存地址以供请求者使用，如适配器功能，用于访问系统内存。 给定请求者使用的特定地址转换格式在与该请求者相关联的设备表条目中预先注册。

公开(公告)号：US20110320675A1

公开(公告)日：2011-12-29

申请号：US12821242

申请日：2010-06-23

申请人： Thomas A. Gregg ,  Gerd K. Bayer ,  David F. Craddock ,  Michael Jung ,  Eric N. Lais ,  Elke G. Nass

发明人： Thomas A. Gregg ,  Gerd K. Bayer ,  David F. Craddock ,  Michael Jung ,  Eric N. Lais ,  Elke G. Nass

IPC分类号： G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/404 ,  G06F2213/0026

摘要： A system for implementing non-standard I/O adapters in a standardized I/O architecture, the system comprising an I/O hub communicatively coupled to an I/O bus and at least one I/O adapter, the I/O hub including logic for implementing a method, the method comprising receiving a request to perform an operation on the I/O adapter from a requester at a requester address, the I/O adapter at a destination address, determining that the request is in a format other than a format supported by the I/O bus, the I/O bus expecting a requester identifier at a first location in a header of the request, reformatting the request into the format supported by the I/O bus, the reformatting comprising storing the requester address, the destination address and an operation code at the first location in the header of the reformatted request, and sending the reformatted request to the I/O adapter.

摘要翻译： 一种用于在标准I / O架构中实现非标准I / O适配器的系统，该系统包括通信地耦合到I / O总线和至少一个I / O适配器的I / O集线器，所述I / O集线器包括 用于实现方法的逻辑，所述方法包括从请求者地址的请求者接收对所述I / O适配器执行操作的请求，所述I / O适配器在目的地地址处，确定所述请求是不是 I / O总线支持的格式，I / O总线期望在请求的头部中的第一位置处的请求者标识符，将请求重新格式化为由I / O总线支持的格式，重新格式化包括存储请求者 地址，目的地地址和重新格式化请求的头部中第一个位置的操作代码，并将重新格式化的请求发送到I / O适配器。

公开(公告)号：US20110320666A1

公开(公告)日：2011-12-29

申请号：US12821239

申请日：2010-06-23

申请人： Thomas A. Gregg ,  David F. Craddock ,  Eric N. Lais

发明人： Thomas A. Gregg ,  David F. Craddock ,  Eric N. Lais

IPC分类号： G06F13/00

CPC分类号： G06F13/4027 ,  G06F13/36 ,  G06F13/385

摘要： A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters, the I/O hub including logic for implementing a method comprising receiving a request from a requester to perform an operation on one of the plurality of I/O adapters. The method further comprising determining that the request is in a format other than a format supported by the I/O bus, determining that the requester requires a completion response for the request, transforming the request into the format supported by the I/O bus, transmitting the request to the I/O adapter, receiving the completion response from the I/O adapter, the completion response comprising an indicator that the request has been completed, the completion response in the format supported by the I/O bus and transmitting the completion response to the requester.

摘要翻译： 一种用于在标准I / O架构中实现非标准输入/输出（I / O）适配器的系统，包括通信地耦合到I / O总线和多个I / O适配器的I / O集线器，I / O集线器，包括用于实现方法的逻辑，该方法包括从请求者接收对所述多个I / O适配器之一执行操作的请求。 该方法还包括确定该请求是不同于I / O总线支持的格式的格式，确定请求者需要该请求的完成响应，将该请求转换成该I / O总线支持的格式， 将所述请求发送到所述I / O适配器，从所述I / O适配器接收完成响应，所述完成响应包括所述请求已经完成的指示符，所述完成响应以所述I / O总线支持的格式发送， 完成响应请求者。

公开(公告)号：US06922755B1

公开(公告)日：2005-07-26

申请号：US09507261

申请日：2000-02-18

申请人： Robert J. Safranek ,  Eric N. Lais

发明人： Robert J. Safranek ,  Eric N. Lais

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0826 ,  G06F12/0831

摘要： A multinode, multiprocessor computer system with distributed shared memory has reduced hardware and improved performance by providing a directory free environment. Without a directory, nodes do not track where cache lines are stored in caches on other nodes. In two-node systems, cache lines are implied to be either on the local node or cached at the remote node or both. Thus, if a local node has a cache miss it is implied that the other node in the system has the cache line. In another aspect, the system allows for “silent rollouts.” In prior distributed memory multiprocessor systems, when a remote node has capacity limitations, it must overwrite (i.e., rollout) a cache line and report to the home node that the rollout occurred. However, the described system allows the remote node to rollout a cache line without reporting to the home node that the rollout occurred. Such a silent rollout can create timing problems because the home node still believes the remote node has a shared copy of the cache line. To solve the timing problems and ensure forward progress, if the remote node requests a cache line and receives an invalidate message, it issues a request for an exclusive copy of the cache line. By requesting an exclusive copy, the remote node is guaranteed to obtain the desired cache line and forward progress is achieved.

摘要翻译： 具有分布式共享内存的多节点，多处理器计算机系统通过提供目录免费环境降低了硬件并提高了性能。 没有目录，节点不跟踪缓存线在其他节点的高速缓存中的存储位置。 在双节点系统中，缓存行隐含在本地节点上或缓存在远程节点上，或两者都是缓存。 因此，如果本地节点具有高速缓存未命中，则暗示系统中的另一个节点具有高速缓存行。 另一方面，该系统允许“静默的卷展栏”。 在现有的分布式存储器多处理器系统中，当远程节点具有容量限制时，它必须覆盖（即，卷起）高速缓存行并向主节点报告该卷展发生。 然而，所描述的系统允许远程节点在不向家庭节点报告卷发的情况下，推出高速缓存行。 这样一个无声的推出可以产生时序问题，因为家庭节点仍然认为远程节点具有高速缓存行的共享副本。 为了解决时序问题并确保前进进度，如果远程节点请求高速缓存行并接收到无效消息，则会发出缓存行专用副本的请求。 通过请求独占副本，远程节点保证获得所需的高速缓存行，并实现向前进展。

公开(公告)号：US08495252B2

公开(公告)日：2013-07-23

申请号：US13007800

申请日：2011-01-17

申请人： Eric N. Lais ,  Gregory M. Nordstrom ,  Steven M. Thurber

发明人： Eric N. Lais ,  Gregory M. Nordstrom ,  Steven M. Thurber

IPC分类号： G06F3/00

CPC分类号： G06F13/404

摘要： A method, system and computer program product are provided for implementing PCI-Express memory domains for single root virtualized devices. A PCI host bridge (PHB) includes a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) are used to associate MMIO domains with PCI memory VF BAR spaces. One MDD is provided for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to the PCI host bridge (PHB). The MDT used with the MDD includes having a number of entries limited to a predefined total number of SRIOV VFs to be configured. A VF BAR Stride, which may be further implemented as a VF BAR Stride Capability Structure, is provided to reduce the number of MDDs required to map SRIOV VF BAR spaces. A particular definition of the MDD is provided to reduce the number of MDDs required to at most one per SRIOV bus segment below a PHB.

摘要翻译： 提供了一种用于实现单根虚拟化设备的PCI-Express存储域的方法，系统和计算机程序产品。 PCI主机桥（PHB）包括内存映射IO（MMIO）域描述符（MDD），MMIO域表（MDT）用于将MMIO域与PCI内存VF BAR空间相关联。 为每个总线段的每个独特的VF BAR空间大小提供一个MDD，将单个根IO虚拟化（SRIOV）设备连接到PCI主机桥（PHB）。 与MDD一起使用的MDT包括许多条目限于要配置的预定义的SRIOV VF的总数。 提供可以进一步实现为VF BAR步幅能力结构的VF BAR Stride，以减少映射SRIOV VF BAR空间所需的MDD数量。 提供了MDD的特定定义，以减少PHB以下每个SRIOV总线段中每个至多一个MDD所需的MDD数量。

公开(公告)号：US08417911B2

公开(公告)日：2013-04-09

申请号：US12821224

申请日：2010-06-23

申请人： David Craddock ,  Thomas A. Gregg ,  Eric N. Lais

发明人： David Craddock ,  Thomas A. Gregg ,  Eric N. Lais

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F3/00

CPC分类号： G06F13/16 ,  G06F2213/0026

摘要： An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory.

摘要翻译： 地址控制器包括位选择器，其接收请求者id的第一部分，并从标识请求功能是SR-IOV设备还是标准PCIe设备的向量中选择一个位。 控制器还包括耦合到比特选择器的选择器，其基于从选择器接收的输入形成由RID的第二部分或地址部分的第一部分组成的输出，以及接收第一部分的地址控制单元 的RID和输出，并且基于此来确定拥有请求功能的LPAR，地址控制单元向存储器提供校正的存储器请求。