公开(公告)号：US6153474A

公开(公告)日：2000-11-28

申请号：US108619

申请日：1998-07-01

申请人： Herbert Lei Ho ,  Radhika Srinivasan ,  Scott D. Halle ,  Erwin Hammerl ,  David M. Dobuzinsky ,  Jack Allan Mandelman ,  Mark Anthony Jaso

发明人： Herbert Lei Ho ,  Radhika Srinivasan ,  Scott D. Halle ,  Erwin Hammerl ,  David M. Dobuzinsky ,  Jack Allan Mandelman ,  Mark Anthony Jaso

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10861 ,  H01L21/76232 ,  H01L27/10832 ,  H01L28/82 ,  Y10S438/973

摘要： The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.

摘要翻译： 本发明包括一种用于增加DRAM芯片上的存储节点中的深沟槽侧壁表面积的方法和系统。 通过倾斜沟槽，电容增加，而不占用半导体芯片上的更多空间。

公开(公告)号：US5792685A

公开(公告)日：1998-08-11

申请号：US667541

申请日：1996-06-21

申请人： Erwin Hammerl ,  Jack A. Mandelman ,  Bernhard Poschenrieder ,  Alvin P. Short ,  Radhika Srinivasan ,  Reinhard J. Stengl ,  Herbert L. Ho

发明人： Erwin Hammerl ,  Jack A. Mandelman ,  Bernhard Poschenrieder ,  Alvin P. Short ,  Radhika Srinivasan ,  Reinhard J. Stengl ,  Herbert L. Ho

IPC分类号： H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10832

摘要： Method for forming three-dimensional device structures comprising a second device formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device.

摘要翻译： 公开了一种用于形成包括形成在第一装置上的第二装置的三维装置结构的方法。 在第一装置上方形成具有单一晶体顶表面的层，以提供用于形成第二装置的有效区域的基座。

公开(公告)号：US5656535A

公开(公告)日：1997-08-12

申请号：US610912

申请日：1996-03-04

申请人： Herbert Ho ,  Radhika Srinivasan ,  Scott D. Halle ,  Erwin Hammerl ,  David M. Dobuzinsky ,  Jack A. Mandelman ,  Mark Anthony Jaso

发明人： Herbert Ho ,  Radhika Srinivasan ,  Scott D. Halle ,  Erwin Hammerl ,  David M. Dobuzinsky ,  Jack A. Mandelman ,  Mark Anthony Jaso

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10861 ,  H01L21/76232 ,  H01L27/10832 ,  H01L28/82 ,  Y10S438/973

摘要： A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.

摘要翻译： 一种在半导体衬底上制造用于深沟槽DRAM的存储节点的简化方法。 该方法包括在衬底的表面中蚀刻沟槽，然后在沟槽的侧壁上形成介电材料层，其顶部部分随后从侧壁去除。 接下来，在侧壁的暴露部分上生长一层氧化物。 然后从侧壁去除该层氧化物的一部分，以便将氧化层定向到距衬底表面预定的距离。 最后，沟槽填充有半导体材料。

公开(公告)号：US5643823A

公开(公告)日：1997-07-01

申请号：US531844

申请日：1995-09-21

申请人： Herbert Ho ,  Erwin Hammerl ,  David M. Dobuzinsky ,  J. Herbert Palm ,  Stephen Fugardi ,  Atul Ajmera ,  James F. Moseman ,  Samuel C. Ramac

发明人： Herbert Ho ,  Erwin Hammerl ,  David M. Dobuzinsky ,  J. Herbert Palm ,  Stephen Fugardi ,  Atul Ajmera ,  James F. Moseman ,  Samuel C. Ramac

IPC分类号： H01L21/76 ,  H01L21/3105 ,  H01L21/318 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/3105 ,  H01L21/32 ,  H01L21/76224 ,  Y10S148/05

摘要： Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. C. for 60 seconds.

摘要翻译： 硅集成电路在浅沟槽隔离（STI）结构中使用氮化硅（Si 3 N 4）的结晶层作为O 2阻挡膜。 与沉积的非晶Si3N4相比，晶体Si3N4降低了电子阱的密度。 此外，可以沉积更大范围的低压化学气相沉积（LPCVD）Si 3 N 4膜，为厚度可控性提供更大的处理窗口。 在720℃至780℃的温度下沉积LPCVD-Si 3 N 4膜。沉积膜处于非晶状态。 随后，在1050℃至1100℃下进行纯氮或氨的高温快速热退火60秒。

公开(公告)号：US5937292A

公开(公告)日：1999-08-10

申请号：US730839

申请日：1996-10-17

申请人： Erwin Hammerl ,  Herb Lei Ho

发明人： Erwin Hammerl ,  Herb Lei Ho

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10861

摘要： A method for forming an oxygen-impervious barrier on the oxide collar of a trench capacitor in a DRAM cell. The process consists of etching a shallow trench into the oxide collar which surrounds the polysilicon trench fill and isolating it from the single crystal semiconducting substrate material of the DRAM cell to a depth which is at least equal to or larger than the width of the oxide collar. A nitride layer with a thickness equal to or thicker than half of the width of the oxide collar is then deposited on the top surface of the freshly excavated oxide collar such that the aforementioned trench is completely filled with this nitride layer, and the entire surfaces of the substrate and polysilicon trench fill are completely covered. The newly formed nitride layer is then selectively overetched in order to completely remove it from the substrate and polysilicon trench fill surfaces, while still maintaining a sufficient thickness of this layer disposed on the oxide collar sufficient to prevent oxygen diffusion into the oxide collar. Alternatively, the nitride layer may be deposited as a thin layer sandwiched between the original oxide collar and an additional thermally deposited oxide layer.

摘要翻译： 一种用于在DRAM单元中的沟槽电容器的氧化物环上形成不透氧屏障的方法。 该方法包括将浅沟槽蚀刻到环绕多晶硅沟槽填充物的氧化物环中，并将其从DRAM单元的单晶半导体衬底材料隔离到至少等于或大于氧化物环的宽度的深度 。 然后将厚度等于或大于氧化物环的宽度的一半的氮化物层沉积在新挖出的氧化物环的顶表面上，使得上述沟槽完全填充有该氮化物层，并且整个表面 衬底和多晶硅沟槽填充被完全覆盖。 然后，新形成的氮化物层被选择性地过蚀刻，以便将其从衬底和多晶硅沟槽填充表面完全去除，同时仍保持设置在氧化物环上的该层的足够厚度足以防止氧气扩散进入氧化物环。 或者，可以将氮化物层沉积成夹在原始氧化物环和附加的热沉积氧化物层之间的薄层。

公开(公告)号：US5828076A

公开(公告)日：1998-10-27

申请号：US727440

申请日：1996-10-17

申请人： Harald Gossner ,  Ignaz Eisele ,  Lothar Risch ,  Erwin Hammerl

发明人： Harald Gossner ,  Ignaz Eisele ,  Lothar Risch ,  Erwin Hammerl

IPC分类号： H01L29/78 ,  B82B1/00 ,  H01L21/20 ,  H01L21/335 ,  H01L29/06 ,  H01L29/10 ,  H01L29/12 ,  H01L29/423

CPC分类号： H01L29/127 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L29/1054 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/78

摘要： In its gate region (10), a silicon MOS technology component has a surface structure (6) having edges and/or vertices at which inversion regions, suitable as quantum wires or quantum dots, are preferentially formed when a gate voltage is applied. The surface structure is preferably formed as a silicon pyramid (6) by local molecular beam epitaxy.

摘要翻译： PCT No.PCT / DE95 / 00448 Sec。 371日期1996年10月17日第 102（e）日期1996年10月17日PCT提交1995年4月4日PCT公布。 WO95 / 28741 PCT出版物 日期1995年10月26日在其栅极区域（10）中，硅MOS技术部件具有具有边缘和/或顶点的表面结构（6），当栅极（10）处优选形成适合作为量子线或量子点的反转区域 施加电压。 表面结构优选通过局部分子束外延形成为硅金字塔（6）。

公开(公告)号：US5747866A

公开(公告)日：1998-05-05

申请号：US785322

申请日：1997-01-21

申请人： Herbert Ho ,  Erwin Hammerl ,  David M. Dobuzinsky ,  Herbert Palm ,  Stephen Fugardi ,  Atul Ajmera ,  James F. Moseman ,  Samuel C. Ramac

发明人： Herbert Ho ,  Erwin Hammerl ,  David M. Dobuzinsky ,  Herbert Palm ,  Stephen Fugardi ,  Atul Ajmera ,  James F. Moseman ,  Samuel C. Ramac

IPC分类号： H01L21/76 ,  H01L21/3105 ,  H01L21/318 ,  H01L21/32 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/3105 ,  H01L21/32 ,  H01L21/76224 ,  Y10S148/05

摘要： Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. for 60 seconds.

摘要翻译： 硅集成电路在浅沟槽隔离（STI）结构中使用氮化硅（Si 3 N 4）的结晶层作为O 2阻挡膜。 与沉积的非晶Si3N4相比，晶体Si3N4降低了电子阱的密度。 此外，可以沉积更大范围的低压化学气相沉积（LPCVD）Si 3 N 4膜，为厚度可控性提供更大的处理窗口。 在720℃至780℃的温度下沉积LPCVD-Si 3 N 4膜。沉积膜处于非晶状态。 随后，在1050℃至1100℃下进行纯氮或氨的高温快速热退火60秒。

公开(公告)号：US5674769A

公开(公告)日：1997-10-07

申请号：US665183

申请日：1996-06-14

申请人： Johann Alsmeier ,  Christine Dehm ,  Erwin Hammerl ,  Reinhard J. Stengl

发明人： Johann Alsmeier ,  Christine Dehm ,  Erwin Hammerl ,  Reinhard J. Stengl

IPC分类号： H01L29/41 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10823

摘要： A method of fabricating sub-GR gates in a deep trench DRAM cell. The method comprises depositing, removing, and selectively etching a plurality of layers which include sacrificial spacers, liners, masking, and resist layers of both semiconducting and non-semiconducting materials on a semiconductor substrate according to specific process flows designed to circumvent the problems associated with prior art sub-GR processes. The method represents an improvement on standard gate conductor processes and provides a device which achieves an up to now unachieved decoupling of channel doping and junction doping.

摘要翻译： 在深沟槽DRAM单元中制造子GR栅极的方法。 该方法包括在半导体衬底上沉积，去除和选择性地蚀刻包括半导体衬底上的半导体和非半导体材料的牺牲隔离物，衬垫，掩模和抗蚀剂层的多个层，所述特定工艺流程旨在规避与 现有技术的子GR过程。 该方法代表了对标准栅极导体工艺的改进，并且提供了实现通道掺杂和结掺杂的迄今未达成的去耦的器件。

公开(公告)号：US5670805A

公开(公告)日：1997-09-23

申请号：US643983

申请日：1996-05-07

申请人： Erwin Hammerl ,  Jack A. Mandelman ,  Herbert L. Ho ,  Junichi Shiozawa ,  Reinhard Johannes Stengl

发明人： Erwin Hammerl ,  Jack A. Mandelman ,  Herbert L. Ho ,  Junichi Shiozawa ,  Reinhard Johannes Stengl

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/10861

摘要： A semiconductor memory device includes a trench formed in a semiconductor substrate. Conductive material is formed in the trench and is insulatively spaced from the semiconductor substrate to form a capacitor. A transfer gate transistor includes source/drain regions formed on a surface of the semiconductor substrate and a control gate which is insulatively spaced from a channel region between the source and drain regions. A buried strap electrically connects the capacitor to one of the source/drain regions of the transfer gate transistor. A portion of the buried strap includes recrystallized silicon.

摘要翻译： 半导体存储器件包括形成在半导体衬底中的沟槽。 导电材料形成在沟槽中并且与半导体衬底绝缘地间隔开以形成电容器。 传输栅极晶体管包括形成在半导体衬底的表面上的源极/漏极区域和与源极区域和漏极区域之间的沟道区域间隔开的控制栅极。 掩埋带将电容器电连接到传输栅极晶体管的源极/漏极区域之一。 掩埋带的一部分包括再结晶硅。

公开(公告)号：US5899724A

公开(公告)日：1999-05-04

申请号：US647392

申请日：1996-05-09

申请人： David Mark Dobuzinsky ,  Stephen Gerard Fugardi ,  Erwin Hammerl ,  Herbert Lei Ho ,  Samuel C. Ramac ,  Alvin Wayne Strong

发明人： David Mark Dobuzinsky ,  Stephen Gerard Fugardi ,  Erwin Hammerl ,  Herbert Lei Ho ,  Samuel C. Ramac ,  Alvin Wayne Strong

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/20

CPC分类号： H01L28/24

摘要： According to the preferred embodiment of the present invention, an improved resistor and method of fabrication is provided. The method for fabricating a resistive element into an integrated circuit semiconductor device comprises the steps of: depositing a dielectric film, such as silicon nitride; depositing a titanium film upon the dielectric film; and annealing the titanium and dielectric films. This causes titanium to be diffused into the dielectric film. This creates a resistive element having a relatively high resistivity. The preferred embodiment method has the advantage of being easily integrated into conventional integrated circuit fabrication techniques.

摘要翻译： 根据本发明的优选实施例，提供一种改进的电阻器和制造方法。 将电阻元件制造成集成电路半导体器件的方法包括以下步骤：沉积诸如氮化硅的介电膜; 在电介质膜上沉积钛膜; 并对钛和介电膜进行退火。 这导致钛扩散到电介质膜中。 这产生具有相对较高电阻率的电阻元件。 优选的实施方式具有易于集成到常规集成电路制造技术中的优点。