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公开(公告)号：US6031876A
公开(公告)日：2000-02-29
申请号：US882668
申请日：1997-06-25
申请人： Dae-Il Oh , Eung-Ryeol Kim , Dae-Hyun Kim , Won-Jin Lee
发明人： Dae-Il Oh , Eung-Ryeol Kim , Dae-Hyun Kim , Won-Jin Lee
CPC分类号： H04L1/0052 , H03M13/4169 , H04L1/0054
摘要： A traceback device of a trellis decoder including a memory for storing survivor path information as much as a decision depth, a multiplexing unit for decoding the survivor path information received from the memorizing unit, and a traceback unit receiving the survivor path information of lower bits decoded by the multiplexing unit and state output of itself, to carry out a state transition and trace back the decoded value of lower bits.
摘要翻译： 一种网格解码器的追溯装置，包括用于存储与存储单元接收的幸存路径信息一样的决策深度的存储器，用于存储幸存路径信息的存储器，以及接收低位解码的幸存路径信息的追溯单元 通过复用单元和其自身的状态输出，执行状态转换并追溯低位的解码值。
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2.发明授权
公开(公告)号：US5959703A
公开(公告)日：1999-09-28
申请号：US902141
申请日：1997-07-30
申请人： Dae-Il Oh , Eung-Ryeol Kim , Dae-Hyun Kim , Won-Jin Lee
发明人： Dae-Il Oh , Eung-Ryeol Kim , Dae-Hyun Kim , Won-Jin Lee
CPC分类号： H04N21/2383 , H04N19/89 , H04N21/4382
摘要： In an error data removing apparatus and method by decoding delay in a DTV system which employs a decoder of the VSB standard, respective segments or respective fields are divided into area 1 and area 2 using a starting point of decoded data as a reference to provide the decoded data of said area 1 section without involving delay and provide the decoded data of said area 2 section by delaying as long as a sync signal. A memory is utilized as the decoded data delay apparatus, and at this time, a value of a counter used for generating an address for reading/writing of the memory is utilized to delay the segment sync signal and field sync signal as required without separately using flip-flop or memory.
摘要翻译： 在采用VSB标准的解码器的DTV系统中解码延迟的误差数据去除装置和方法中，使用解码数据的起始点将各个段或各个区域划分为区域1和区域2作为参考，以提供 所述区域1部分的解码数据而不涉及延迟，并且通过延迟长达同步信号来提供所述区域2部分的解码数据。 使用存储器作为解码数据延迟装置，此时，用于产生用于存储器的读/写的地址的计数器的值被用来根据需要延迟段同步信号和场同步信号，而不需要单独使用 触发器或内存。
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