公开(公告)号：US08639205B2

公开(公告)日：2014-01-28

申请号：US12052657

申请日：2008-03-20

Applicant: Junxiong Deng ,  Aristotele Hadjichristos ,  Aleksandar Tasic ,  Frederic Bossu

Inventor： Junxiong Deng ,  Aristotele Hadjichristos ,  Aleksandar Tasic ,  Frederic Bossu

IPC: H04B1/26

CPC classification number: H04W52/0206 ,  H03G3/20 ,  H04B1/16

Abstract: An exemplary embodiment disclosed comprises a mixer having a plurality of input leads; a first degenerative impedance element coupled to a first input lead of the mixer; a second degenerative impedance element coupled to a second input lead of the mixer; and a local oscillator (LO) system comprising a plurality of duty cycle modes to generate a LO signal for the mixer, the local oscillator system operates in a first duty cycle based on a first gain state of the mixer, and in a second duty cycle based on a second gain state of the mixer.

Abstract translation: 公开的示例性实施例包括具有多个输入引线的混合器; 耦合到混合器的第一输入引线的第一退化阻抗元件; 耦合到混合器的第二输入引线的第二退化阻抗元件; 以及本地振荡器（LO）系统，其包括多个占空比模式以产生混频器的LO信号，本地振荡器系统基于混频器的第一增益状态在第一占空比中工作，并且在第二占空比 基于混频器的第二增益状态。

公开(公告)号：US08615205B2

公开(公告)日：2013-12-24

申请号：US12259178

申请日：2008-10-27

Applicant: Ojas M. Choksi ,  Frederic Bossu

Inventor： Ojas M. Choksi ,  Frederic Bossu

IPC: H03C1/62

CPC classification number: H04L5/1461 ,  H03D3/009 ,  H03M1/1019 ,  H03M1/66 ,  H04L27/0014 ,  H04L2027/0016 ,  H04L2027/0018 ,  H04L2027/0024

Abstract: Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed.

Abstract translation: 提供了用于减少通信发射机或接收机的同相（I）和正交（Q）信道之间的失配的技术。 在示例性实施例中，施加单独的电压以在I通道的混频器中与Q通道的混频器偏置晶体管的栅极或体积。 在另一个示例性实施例中，施加单独的电压以偏置与每个通道相关联的跨阻抗放大器的共模参考电压。 还提供了用于导出偏置电压以最小化接收或发射信号中测量的残留边带或者优化接收或发射信号的其它参数的技术。 还公开了使用双向和单向电流数模转换器（DAC）产生单独偏置电压的技术。

公开(公告)号：US20130109330A1

公开(公告)日：2013-05-02

申请号：US13282354

申请日：2011-10-26

Applicant: Gurkanwal Singh Sahota ,  Frederic Bossu ,  Berke Cetinoneri

Inventor： Gurkanwal Singh Sahota ,  Frederic Bossu ,  Berke Cetinoneri

IPC: H04B1/40

CPC classification number: H04B1/525 ,  H04B1/581

Abstract: Exemplary embodiments are directed to impedance balancing within a transceiver. A device may include a transformer having a first side coupled to a transmit path and a second side coupled to a receive path. Further, the device may include an antenna tuning network coupled to a first portion of the first side and configured for coupling to an antenna. The device may also include an adjustment unit coupled to a second portion of the first side and configured for being adjusted to enable an impedance at the adjustment unit to be substantially equal to an impedance at the antenna tuning network.

Abstract translation: 示例性实施例涉及收发器内的阻抗平衡。 设备可以包括具有耦合到发射路径的第一侧和耦合到接收路径的第二侧的变压器。 此外，设备可以包括耦合到第一侧的第一部分并被配置为耦合到天线的天线调谐网络。 该装置还可以包括耦合到第一侧的第二部分并被配置为被调整以使调节单元处的阻抗基本上等于天线调谐网络处的阻抗的调节单元。

公开(公告)号：US20100244971A1

公开(公告)日：2010-09-30

申请号：US12436265

申请日：2009-05-06

Applicant: Kevin H. Wang ,  Saru Palakurty ,  Frederic Bossu

Inventor： Kevin H. Wang ,  Saru Palakurty ,  Frederic Bossu

IPC: H03L7/099

CPC classification number: G04F10/005

Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.

Abstract translation: 描述具有小于一个逆变器延迟的精细分辨率的时间 - 数字转换器（TDC）。 在示例性设计中，TDC包括第一和第二延迟路径，延迟单元和相位计算单元。 第一延迟路径接收第一输入信号和第一参考信号并提供第一输出。 第二延迟路径接收第二输入信号和第二参考信号并提供第二输出。 延迟单元相对于第一输入信号延迟第二输入信号或相对于第一参考信号延迟第二参考信号，例如延迟半个逆变器延迟。 相位计算单元接收第一和第二输出，并且在输入信号和参考信号之间提供相位差。 可以执行校准以获得第一和第二延迟路径的精确定时。

公开(公告)号：US20100240323A1

公开(公告)日：2010-09-23

申请号：US12407700

申请日：2009-03-19

Applicant: Dongjiang Qiao ,  Frederic Bossu

Inventor： Dongjiang Qiao ,  Frederic Bossu

IPC: H04B1/40 ,  H03B19/00

CPC classification number: G06F1/06 ,  H03K23/667 ,  H03K23/68

Abstract: A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a single-ended frequency divider and a synchronization circuit. The single-ended frequency divider divides the clock signal in frequency and provides first and second single-ended signals, which may be complementary signals having timing skew. The synchronization circuit resamples the first and second single-ended signals based on the clock signal and provides differential output signals having reduced timing skew. In one exemplary design, the synchronization circuit includes first and second switches and first and second inverters. The first switch and the first inverter form a first sample-and-hold circuit or a first latch that resamples the first single-ended signal. The second switch and the second inverter form a second sample-and-hold circuit or a second latch that resamples the second single-ended signal.

Abstract translation: 描述了可以将时钟信号分频并提供具有良好信号特性的差分输出信号的同步分频器。 在一个示例性设计中，同步分频器包括单端分频器和同步电路。 单端分频器分频时钟信号，并提供第一和第二单端信号，这可能是具有定时偏移的互补信号。 同步电路基于时钟信号重新采样第一和第二单端信号，并提供具有减小的定时偏差的差分输出信号。 在一个示例性设计中，同步电路包括第一和第二开关以及第一和第二逆变器。 第一开关和第一反相器形成第一采样保持电路或重新采样第一单端信号的第一锁存器。 第二开关和第二反相器形成第二采样保持电路或重新采样第二单端信号的第二锁存器。

公开(公告)号：US09362958B2

公开(公告)日：2016-06-07

申请号：US13411444

申请日：2012-03-02

Applicant: Prasad Srinivasa Siva Gudem ,  Gurkanwal Singh Sahota ,  Li-chung Chang ,  Christian Holenstein ,  Frederic Bossu

Inventor： Prasad Srinivasa Siva Gudem ,  Gurkanwal Singh Sahota ,  Li-chung Chang ,  Christian Holenstein ,  Frederic Bossu

IPC: H04B1/00 ,  H04B7/04

CPC classification number: H04B1/0057 ,  H04B7/04

Abstract: A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a single-chip signal splitting carrier aggregation receiver architecture. The single-chip signal splitting carrier aggregation receiver architecture includes a primary antenna, a secondary antenna and a transceiver chip. The single-chip signal splitting carrier aggregation receiver architecture reuses a simultaneous hybrid dual receiver path.

Abstract translation: 描述了被配置为接收多载波信号的无线通信设备。 无线通信设备包括单芯片信号分离载波聚合接收机架构。 单芯片信号分离载波聚合接收机架构包括主天线，辅助天线和收发芯片。 单芯片信号分离载波聚合接收机架构重用同步混合双接收机路径。

公开(公告)号：US09083441B2

公开(公告)日：2015-07-14

申请号：US13282354

申请日：2011-10-26

Applicant: Gurkanwal Singh Sahota ,  Frederic Bossu ,  Berke Cetinoneri

Inventor： Gurkanwal Singh Sahota ,  Frederic Bossu ,  Berke Cetinoneri

IPC: H03C1/52 ,  H04B1/525 ,  H04B1/58

CPC classification number: H04B1/525 ,  H04B1/581

Abstract: Exemplary embodiments are directed to impedance balancing within a transceiver. A device may include a transformer having a first side coupled to a transmit path and a second side coupled to a receive path. Further, the device may include an antenna tuning network coupled to a first portion of the first side and configured for coupling to an antenna. The device may also include an adjustment unit coupled to a second portion of the first side and configured for being adjusted to enable an impedance at the adjustment unit to be substantially equal to an impedance at the antenna tuning network.

Abstract translation: 示例性实施例涉及收发器内的阻抗平衡。 设备可以包括具有耦合到发射路径的第一侧和耦合到接收路径的第二侧的变压器。 此外，设备可以包括耦合到第一侧的第一部分并被配置为耦合到天线的天线调谐网络。 该装置还可以包括耦合到第一侧的第二部分并被配置为被调整以使调节单元处的阻抗基本上等于天线调谐网络处的阻抗的调节单元。

公开(公告)号：US08929840B2

公开(公告)日：2015-01-06

申请号：US12209164

申请日：2008-09-11

Applicant: Sankaran Aniruddhan ,  Chiewcharn Narathong ,  Sriramgopal Sridhara ,  Ravi Sridhara ,  Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

Inventor： Sankaran Aniruddhan ,  Chiewcharn Narathong ,  Sriramgopal Sridhara ,  Ravi Sridhara ,  Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

IPC: H04B1/02 ,  H04B1/06 ,  H04B7/00 ,  H04B1/26 ,  H03D7/16 ,  H03D7/14 ,  H03G3/30

CPC classification number: H03D7/166 ,  H03D7/1441 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0025 ,  H03G3/3052

Abstract: Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.

Abstract translation: 公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。 在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。 在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。 公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

公开(公告)号：US20120081185A1

公开(公告)日：2012-04-05

申请号：US13316621

申请日：2011-12-12

Applicant: Kevin H. Wang ,  Saru Palakurty ,  Frederic Bossu

Inventor： Kevin H. Wang ,  Saru Palakurty ,  Frederic Bossu

IPC: H03L7/093 ,  H03D13/00

CPC classification number: G04F10/005

Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.

Abstract translation: 描述具有小于一个逆变器延迟的精细分辨率的时间 - 数字转换器（TDC）。 在示例性设计中，TDC包括第一和第二延迟路径，延迟单元和相位计算单元。 第一延迟路径接收第一输入信号和第一参考信号并提供第一输出。 第二延迟路径接收第二输入信号和第二参考信号并提供第二输出。 延迟单元相对于第一输入信号延迟第二输入信号或相对于第一参考信号延迟第二参考信号，例如延迟半个逆变器延迟。 相位计算单元接收第一和第二输出，并且在输入信号和参考信号之间提供相位差。 可以执行校准以获得第一和第二延迟路径的精确定时。

公开(公告)号：US07825703B2

公开(公告)日：2010-11-02

申请号：US12193693

申请日：2008-08-18

Applicant: Dongjiang Qiao ,  Frederic Bossu

Inventor： Dongjiang Qiao ,  Frederic Bossu

IPC: H03B19/00

CPC classification number: H03L7/183 ,  H03H11/265 ,  H03K23/42 ,  H03L7/0812

Abstract: A local oscillator includes a programmable frequency divider coupled to the output of a VCO. The frequency divider can be set to frequency divide by three. Regardless of the divisor, the frequency divider outputs quadrature signals (I, Q) that differ from each other in phase by ninety degrees. To divide by three, the frequency divider includes a divide-by-three frequency divider. The divide-by-three frequency divider includes a divide-by-three circuit, a delay circuit, and a feedback circuit. The divide-by-three circuit frequency divides a signal from the VCO and generates therefrom three signals C, A′ and B that differ from each other in phase by one hundred twenty degrees. The delay circuit delays signal A′ to generate a delayed version A of the signal A′. The feedback circuit controls the delay circuit such that the delayed version A (I) is ninety degrees out of phase with respect to the signal C (Q).

Abstract translation: 本地振荡器包括耦合到VCO的输出的可编程分频器。 分频器可以设置为三分频。 除了除数以外，分频器输出相位相差九十度的正交信号（I，Q）。 为了除以3，分频器包括一个除以三分频器。 除以三分频器包括三分之一电路，延迟电路和反馈电路。 三分频电路分频来自VCO的信号，从而产生三相彼此相差一百二十度的信号C，A'和B。 延迟电路延迟信号A'以产生信号A'的延迟版本A. 反馈电路控制延迟电路，使得延迟版本A（I）相对于信号C（Q）相差90度。