公开(公告)号：US08543959B2

公开(公告)日：2013-09-24

申请号：US13087464

申请日：2011-04-15

申请人： Gary Dale Carpenter ,  Alan James Drake ,  Eren Kursun

发明人： Gary Dale Carpenter ,  Alan James Drake ,  Eren Kursun

IPC分类号： G06F17/50

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method, system, and computer program product for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A first candidate chip is selected from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit. A part of a 3D performance determinant is activated in the first candidate chip. A value of a performance parameter is measured for a set of operating conditions. A stacked performance value is computed for the first candidate chip using the value. A subset of the set of candidate chips is stacked in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.

摘要翻译： 在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的方法，系统和计算机程序产品。 从用于堆叠的候选芯片的集合中选择第一候选芯片，所述候选芯片组中的每个候选芯片包括集成电路。 在第一候选芯片中激活3D性能决定因素的一部分。 对于一组操作条件测量性能参数的值。 使用该值计算第一候选芯片的堆叠性能值。 所述候选芯片组的子集被堆叠在堆叠中，所述子集包括第一候选芯片，使得当以第一顺序堆叠时子集的性能参数的组合值在所述性能的值的确定范围内 参数。

公开(公告)号：US06931561B2

公开(公告)日：2005-08-16

申请号：US09978357

申请日：2001-10-16

申请人： Gary Dale Carpenter ,  Tung Nguyen Pham

发明人： Gary Dale Carpenter ,  Tung Nguyen Pham

IPC分类号： G06F5/06 ,  H04L7/02 ,  G06F1/12 ,  H04L7/00

CPC分类号： G06F5/06 ,  H04L7/02

摘要： Interfacing circuitry for asynchronously transferring data between a high-speed clock domain and a low-speed clock domain is provided. The interfacing circuitry is divided into halves, with one half being synchronized to a first clock and the second half being synchronized to a second clock. The first half and the second half are mirror images of each other. Each half has at least one storage component, such as a register and a flip-flop, for storing a valid bit as well as data, and at least one multiplexer component for gating the storage component. The valid bit is used to control the multiplexer at a receiving half. When transferring from a high-speed clock domain to a low-speed clock domain, the high-speed clock domain may probe the received data and/or the valid bit stored in the low-speed clock domain before the high-speed clock domain sends additional data.

摘要翻译： 提供了在高速时钟域和低速时钟域之间异步传输数据的接口电路。 接口电路被分成两半，其中一半与第一时钟同步，而后半部分与第二时钟同步。 上半场和下半场是彼此的镜像。 每一半具有用于存储有效位和数据的至少一个存储组件，例如寄存器和触发器，以及用于门控存储组件的至少一个多路复用器组件。 有效位用于在接收端控制多路复用器。 当从高速时钟域传输到低速时钟域时，高速时钟域可以在高速时钟域发送之前探测存储在低速时钟域中的接收数据和/或有效位 附加数据。

公开(公告)号：US06717452B2

公开(公告)日：2004-04-06

申请号：US10159484

申请日：2002-05-30

申请人： Gary Dale Carpenter ,  Kevin John Nowka

发明人： Gary Dale Carpenter ,  Kevin John Nowka

IPC分类号： H03L500

CPC分类号： H03K19/018521 ,  H03K3/356008

摘要： A level shifter having a data input node, a first inverter having its input connected to the data input node, a second inverter connected to an output of the first inverter, a data output node, a latch having its output connected to the data output node, a first NFET connected between an input of the latch and a ground potential, and having its gate electrode connected to an output of the second inverter, and a second NFET connected between the data output node and the ground potential, and having its gate electrode connected to the output of the first inverter. The level shifter provides for a conversion of a data signal from a power supply domain of 1.8 volts to one of 3.3 volts.

摘要翻译： 具有数据输入节点的电平移位器，具有连接到数据输入节点的输入的第一反相器，连接到第一反相器的输出的第二反相器，数据输出节点，其输出连接到数据输出节点的锁存器 连接在所述锁存器的输入端和接地电位之间并且其栅电极连接到所述第二反相器的输出的第一NFET以及连接在所述数据输出节点和所述地电位之间的第二NFET，并且具有其栅电极 连接到第一个变频器的输出。 电平转换器提供将数据信号从1.8伏的电源域转换为3.3伏特之一的转换。

公开(公告)号：US06266743B1

公开(公告)日：2001-07-24

申请号：US09259365

申请日：1999-02-26

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

IPC分类号： G06F1200

CPC分类号： G06F12/082 ,  G06F12/12

摘要： A method and system for providing an eviction protocol within a non-uniform memory access (NUMA) computer system are disclosed. A NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to a request for evicting an entry from a sparse directory, an non-intervention writeback request is sent to a node having the modified cache line when the entry is associated with a modified cache line. After the data from the modified cache line has been written back to a local system memory of the node, the entry can then be evicted from the sparse directory. If the entry is associated with a shared line, an invalidation request is sent to all nodes that the directory entry indicates may hold a copy of the line. Once all invalidations have been acknowledged, the entry can be evicted from the sparse directory.

摘要翻译： 公开了一种用于在非均匀存储器访问（NUMA）计算机系统内提供逐出协议的方法和系统。 NUMA计算机系统包括耦合到互连的至少两个节点。 两个节点中的每一个包括本地系统存储器。 响应于从稀疏目录驱逐条目的请求，当该条目与修改的高速缓存行相关联时，不干预回写请求被发送到具有修改的高速缓存行的节点。 在来自修改的高速缓存行的数据已经被写回节点的本地系统存储器之后，该条目然后可以从稀疏目录中被逐出。 如果条目与共享线路相关联，则将无效请求发送到目录条目指示的所有节点可能保存该线路的副本。 一旦所有的无效被确认，该条目可以从稀疏目录中被逐出。

公开(公告)号：US06226718B1

公开(公告)日：2001-05-01

申请号：US09259379

申请日：1999-02-26

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

IPC分类号： G06F1202

CPC分类号： G06F12/0813

摘要： A method for avoiding livelocks due to stale exclusive/modified directory entries within a non-uniform memory access (NUMA) computer system is disclosed. A NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to an attempt by a processor of a first node to read a cache line at substantially the same time as a processor of a second node attempts to access the same cache line, wherein the cache line has been silently cast out from a cache memory within the second node even though a coherency directory within the node still indicates the cache line is held exclusively in the second node, the processor of the second node is allowed to access the cache line only if the second node is an owning node of the cache line. The processor of the first node is then allowed to access the cache line.

摘要翻译： 公开了一种用于避免由于在非均匀存储器存取（NUMA）计算机系统内的过时的独占/修改的目录条目引起的活动锁定的方法。 NUMA计算机系统包括耦合到互连的至少两个节点。 两个节点中的每一个包括本地系统存储器。 响应于第一节点的处理器尝试在与第二节点的处理器尝试访问相同的高速缓存行的基本上相同的时间读取高速缓存行，其中高速缓存行已经从高速缓冲存储器 即使在节点内的一致性目录仍然指示高速缓存行仅在第二节点中被保留在第二节点内，则仅当第二节点是高速缓存的所有节点时才允许第二节点的处理器访问高速缓存行 线。 然后允许第一个节点的处理器访问高速缓存行。

公开(公告)号：US06178472B1

公开(公告)日：2001-01-23

申请号：US09097331

申请日：1998-06-15

申请人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F1312

CPC分类号： G06F7/78

摘要： A queue includes a data multiplexer having an output and at least two inputs and a plurality of data latches. The data latches include at least a first data latch and a second data latch, which each have a data input and a data output. The data output of the first data latch is coupled to a first input of the data multiplexer, and the output of the data multiplexer is coupled to the data input of the second data latch. A data value to be stored in the queue is received at a second input to the data multiplexer. In response to one or more control signals, the data value is latched into at least one of the first and second data latches, thereby storing the data value in the queue. Depending upon the design of the control logic, the queue can implement either first in, first out (FIFO) or last in, first out (LIFO) behavior.

摘要翻译： 队列包括具有输出和至少两个输入和多个数据锁存器的数据多路复用器。 数据锁存器至少包括第一数据锁存器和第二数据锁存器，每个锁存器具有数据输入和数据输出。 第一数据锁存器的数据输出耦合到数据多路复用器的第一输入端，并且数据多路复用器的输出耦合到第二数据锁存器的数据输入端。 要存储在队列中的数据值在第二输入处被接收到数据多路复用器。 响应于一个或多个控制信号，数据值被锁存到第一和第二数据锁存器中的至少一个中，从而将数据值存储在队列中。 根据控制逻辑的设计，队列可以先进先出（FIFO）或最后进先出（LIFO）行为。

公开(公告)号：US6115804A

公开(公告)日：2000-09-05

申请号：US248503

申请日：1999-02-10

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

IPC分类号： G06F12/08 ,  G06F15/00

CPC分类号： G06F12/0813

摘要： A non-uniform memory access (NUMA) computer system includes first and second processing nodes that are each coupled to a node interconnect. The first processing node includes a system memory and first and second processors that each have a respective one of first and second cache hierarchies, which are coupled for communication by a local interconnect. The second processing node includes at least a system memory and a third processor having a third cache hierarchy. The first cache hierarchy and the third cache hierarchy are permitted to concurrently store an unmodified copy of a particular cache line in a Recent coherency state from which the copy of the particular cache line can be sourced by shared intervention. In response to a request for the particular cache line by the second cache hierarchy, the first cache hierarchy sources a copy of the particular cache line to the second cache hierarchy by shared intervention utilizing communication on only the local interconnect and without communication on the node interconnect.

摘要翻译： 非均匀存储器访问（NUMA）计算机系统包括第一和第二处理节点，每个处理节点都耦合到节点互连。 第一处理节点包括系统存储器和第一和第二处理器，每个处理器具有第一和第二高速缓存层级中的相应一个，其被耦合用于通过局部互连进行通信。 第二处理节点至少包括系统存储器和具有第三高速缓存层级的第三处理器。 允许第一高速缓存层级和第三高速缓存层次结构将特定高速缓存行的未修改副本并入存储在最近的一致性状态中，通过共享干预可以从特定高速缓存行的副本提供特定高速缓存行的副本。 响应于通过第二高速缓存层次结构对特定高速缓存线的请求，第一高速缓存层级通过仅在局部互连上的通信的共享干预将特定高速缓存行的副本提供给第二高速缓存层级，并且在节点互连上没有通信 。

公开(公告)号：US6088750A

公开(公告)日：2000-07-11

申请号：US247536

申请日：1999-02-10

申请人： Daniel Paul Beaman ,  Gary Dale Carpenter ,  Mark Edward Dean ,  Wendel Glenn Voigt

发明人： Daniel Paul Beaman ,  Gary Dale Carpenter ,  Mark Edward Dean ,  Wendel Glenn Voigt

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F13/40

CPC分类号： G06F13/4018

摘要： A data processing system is disclosed which includes a first processor having an m-byte data width, an n-byte data bus, where n is less than m, and a second processor electrically coupled to the bus which performs bus transactions utilizing n-byte packets of data. An adaptor is electrically coupled between the first processor and the bus which converts n-byte packets of data input from the bus to m-byte packets of data, and converts m-byte packets of data input from the first processor to n-byte packets of data, thereby enabling the first processor to transmit data to and receive data from the bus utilizing m-byte packets of data. In a second aspect of the present invention, a method and system are provided for arbitrating between two bus masters having disparate bus acquisition protocols. In response to a second bus master asserting a bus request when a first bus master controls the bus, control of the bus is removed from the first bus master. Thereafter, in response to a signal transmitted from an arbitration control unit to the first bus master instructing the first bus master to terminate its bus transactions, control of the bus is granted to the second bus master. In response to the second bus master terminating its bus request, control of the bus is granted to the first bus master and a signal is transmitted from the arbitration control unit to the first bus master acknowledging the grant of control.

摘要翻译： 公开了一种数据处理系统，其包括具有m字节数据宽度的第一处理器，n小于m的n字节数据总线，以及电耦合到总线的第二处理器，其使用n字节执行总线事务 数据包数据。 适配器电耦合在第一处理器和总线之间，其将从总线输入的数据的n字节数据转换为数据的m字节数据包，并将从第一处理器输入的数据的m字节数据包转换为n字节数据包 从而使得第一处理器能够利用m字节的数据分组向总线发送数据并从总线接收数据。 在本发明的第二方面中，提供了一种用于在具有不同总线获取协议的两个总线主机之间进行仲裁的方法和系统。 响应于第二总线主控器在第一总线主控器控制总线时断言总线请求，总线的控制从第一总线主控器被移除。 此后，响应于从仲裁控制单元发送到第一总线主机的信号，指示第一总线主机终止其总线事务，总线的控制被授予第二总线主机。 响应于第二总线主机终止其总线请求，总线的控制被授予第一总线主机，并且信号从仲裁控制单元发送到确认授权控制的第一总线主机。

公开(公告)号：US6085293A

公开(公告)日：2000-07-04

申请号：US135283

申请日：1998-08-17

申请人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F12/16

CPC分类号： G06F12/0813 ,  G06F2212/2542

摘要： A non-uniform memory access (NUMA) computer system includes a node interconnect and a plurality of processing nodes that each contain at least one processor, a local interconnect, a local system memory, and a node controller coupled to both a respective local interconnect and the node interconnect. According to the method of the present invention, a communication transaction is transmitted on the node interconnect from a local processing node to a remote processing node. In response to receipt of the communication transaction by the remote processing node, a response including a coherency response field is transmitted on the node interconnect from the remote processing node to the local processing node. In response to receipt of the response at the local processing node, a request is issued on the local interconnect of the local processing node concurrently with a determination of a coherency response indicated by the coherency response field.

摘要翻译： 不均匀存储器访问（NUMA）计算机系统包括节点互连和多个处理节点，每个处理节点包含至少一个处理器，本地互连，本地系统存储器和耦合到相应的本地互连和 节点互连。 根据本发明的方法，在节点互连上从本地处理节点向远程处理节点发送通信事务。 响应于远程处理节点接收到通信事务，在节点互连上从远程处理节点向本地处理节点发送包括一致性响应字段的响应。 响应于在本地处理节点处的响应的接收，在本地处理节点的本地互连上同时确定由相关性响应字段指示的一致性响应的请求。

公开(公告)号：US5898857A

公开(公告)日：1999-04-27

申请号：US354701

申请日：1994-12-13

申请人： Daniel Paul Beaman ,  Gary Dale Carpenter ,  Mark Edward Dean ,  Wendel Glenn Voigt

发明人： Daniel Paul Beaman ,  Gary Dale Carpenter ,  Mark Edward Dean ,  Wendel Glenn Voigt

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F13/00 ,  G06F15/177

CPC分类号： G06F13/4018

摘要： A data processing system is disclosed which includes a first processor having an m-byte data width, an n-byte data bus, where n is less than m, and a second processor electrically coupled to the bus which performs bus transactions utilizing n-byte packets of data. An adaptor is electrically coupled between the first processor and the bus which converts n-byte packets of data input from the bus to m-byte packets of data, and converts m-byte packets of data input from the first processor to n-byte packets of data, thereby enabling the first processor to transmit data to and receive data from the bus utilizing m-byte packets of data. In a second aspect of the present invention, a method and system are provided for arbitrating between two bus masters having disparate bus acquisition protocols. In response to a second bus master asserting a bus request when a first bus master controls the bus, control of the bus is removed from the first bus master. Thereafter, in response to a signal transmitted from an arbitration control unit to the first bus master instructing the first bus master to terminate its bus transactions, control of the bus is granted to the second bus master. In response to the second bus master terminating its bus request, control of the bus is granted to the first bus master and a signal is transmitted from the arbitration control unit to the first bus master acknowledging the grant of control.

摘要翻译： 公开了一种数据处理系统，其包括具有m字节数据宽度的第一处理器，n小于m的n字节数据总线，以及电耦合到总线的第二处理器，其使用n字节执行总线事务 数据包数据。 适配器电耦合在第一处理器和总线之间，其将从总线输入的数据的n字节数据转换为数据的m字节数据包，并将从第一处理器输入的数据的m字节数据包转换为n字节数据包 从而使得第一处理器能够利用m字节的数据分组向总线发送数据并从总线接收数据。 在本发明的第二方面中，提供了一种用于在具有不同总线获取协议的两个总线主机之间进行仲裁的方法和系统。 响应于第二总线主控器在第一总线主控器控制总线时断言总线请求，总线的控制从第一总线主控器被移除。 此后，响应于从仲裁控制单元发送到第一总线主机的信号，指示第一总线主机终止其总线事务，总线的控制被授予第二总线主机。 响应于第二总线主机终止其总线请求，总线的控制被授予第一总线主机，并且信号从仲裁控制单元发送到确认授权控制的第一总线主机。