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公开(公告)号：US20120185815A1
公开(公告)日：2012-07-19
申请号：US13427516
申请日：2012-03-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译： 本公开涉及一种用于提取电路设计的信息的方法。 该方法可以利用增量提取处理来提取电路设计的一部分的信息。 该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。 增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。 该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。
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公开(公告)号：US08612918B2
公开(公告)日：2013-12-17
申请号：US13427486
申请日：2012-03-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method includes establishing a reflexive relationship between a plurality of design shapes corresponding to a plurality of circuit components in the circuit design. The method includes receiving a design change for at least one design shape of the plurality of design shapes. The method includes identifying a set of changed shapes, a set of affected shapes, and a set of involved shapes. The method includes extracting at least one of a capacitance, an inductance or a resistance for the updated circuit design based on at least one of the set of changed shapes, the set of affected shapes and the set of involved shapes. The method includes updating the plurality of circuit components in the circuit design based on at least one of the set of changed shapes and the set of affected shapes.
摘要翻译： 本公开涉及一种用于提取电路设计的信息的方法。 该方法包括在与电路设计中的多个电路部件相对应的多个设计形状之间建立反射关系。 该方法包括接收多个设计形状的至少一个设计形状的设计变化。 该方法包括识别一组改变的形状，一组受影响的形状以及一组涉及的形状。 该方法包括基于变化的形状，受影响的形状的集合和所涉及的形状的集合中的至少一个来提取用于更新的电路设计的电容，电感或电阻中的至少一个。 所述方法包括基于所述一组改变的形状和所述一组受影响的形状中的至少一个来更新所述电路设计中的所述多个电路部件。
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公开(公告)号：US08539428B2
公开(公告)日：2013-09-17
申请号：US13427516
申请日：2012-03-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译： 本公开涉及一种用于提取电路设计的信息的方法。 该方法可以利用增量提取处理来提取电路设计的一部分的信息。 该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。 增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。 该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。
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公开(公告)号：US20120180013A1
公开(公告)日：2012-07-12
申请号：US13427486
申请日：2012-03-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method includes establishing a reflexive relationship between a plurality of design shapes corresponding to a plurality of circuit components in the circuit design. The method includes receiving a design change for at least one design shape of the plurality of design shapes. The method includes identifying a set of changed shapes, a set of affected shapes, and a set of involved shapes. The method includes extracting at least one of a capacitance, an inductance or a resistance for the updated circuit design based on at least one of the set of changed shapes, the set of affected shapes and the set of involved shapes. The method includes updating the plurality of circuit components in the circuit design based on at least one of the set of changed shapes and the set of affected shapes.
摘要翻译： 本公开涉及一种用于提取电路设计的信息的方法。 该方法包括在与电路设计中的多个电路部件相对应的多个设计形状之间建立反射关系。 该方法包括接收多个设计形状的至少一个设计形状的设计变化。 该方法包括识别一组改变的形状，一组受影响的形状以及一组涉及的形状。 该方法包括基于变化的形状，受影响的形状的集合和所涉及的形状的集合中的至少一个来提取用于更新的电路设计的电容，电感或电阻中的至少一个。 所述方法包括基于所述一组改变的形状和所述一组受影响的形状中的至少一个来更新所述电路设计中的所述多个电路部件。
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公开(公告)号：US20100251198A1
公开(公告)日：2010-09-30
申请号：US12415266
申请日：2009-03-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译： 本公开涉及一种用于提取电路设计的信息的方法。 该方法可以利用增量提取处理来提取电路设计的一部分的信息。 该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。 增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。 该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。
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公开(公告)号：US08645899B2
公开(公告)日：2014-02-04
申请号：US12415266
申请日：2009-03-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.
摘要翻译： 本公开涉及一种用于提取电路设计的信息的方法。 该方法可以利用增量提取处理来提取电路设计的一部分的信息。 该部分的提取结果可以与先前提取的结果合并，以获得等同于提取整个电路设计的结果。 增量提取过程可以识别一组改变的形状，一组受影响的形状以及一组涉及的提取形状。 该方法还可以将电路设计分成多个区域，其中两个或更多个区域可以并行处理。
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