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公开(公告)号：US20110311825A1
公开(公告)日：2011-12-22
申请号：US12820870
申请日：2010-06-22
申请人： Maxime Darnon , Gerald W. Gibson , Pratik P. Joshi , Ryan M. Martin , Ying Zhang
发明人： Maxime Darnon , Gerald W. Gibson , Pratik P. Joshi , Ryan M. Martin , Ying Zhang
IPC分类号： B32B5/28
CPC分类号： C23C16/26 , C23C16/56 , H01J9/025 , H01J2201/30469 , H01L21/28562 , H01L21/31138 , H01L21/76837 , H01L21/76885 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10T428/30 , H01L2924/00
摘要： The present disclosure relates to a method for selectively etching-back a polymer matrix to expose tips of carbon nanotubes comprising: a. growing carbon nanotubes on a conductive substrate; b. filling the gap around the carbon nanotubes with a polymeric fill matrix comprising at least one latent photoacid generator; and c. selectively etching-back the polymeric fill matrix to expose tips of the carbon nanotubes.
摘要翻译： 本公开涉及一种用于选择性地蚀回聚合物基质以暴露碳纳米管尖端的方法，其包括：a。 在导电基底上生长碳纳米管; b。 用包含至少一个潜在光酸产生剂的聚合物填充基质填充碳纳米管周围的间隙; 和c。 选择性地回蚀聚合物填充基质以暴露碳纳米管的尖端。
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公开(公告)号：US07332775B2
公开(公告)日：2008-02-19
申请号：US11542864
申请日：2006-10-04
IPC分类号： H01L31/119 , H01L21/336
CPC分类号： H01L21/76897 , H01L29/665 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.
摘要翻译： 在栅电极结构的顶表面上方突出的突出间隔物在用于形成自对准接触的蚀刻工艺期间提供增强的栅电极的暴露电阻。 可以使用非晶碳牺牲层作为图案化栅极电极结构的顶层来形成突出间隔物。 电介质间隔物与栅电极结构一起形成，包括在牺牲无定形碳层的旁边。 电介质隔离层基本上延伸到无定形碳层的顶部。 然后去除无定形碳层，使得剩余的栅极结构包括具有在剩余栅极结构的顶表面上方突出的突出部分的电介质间隔物。 可以在栅极结构上形成氮化物层。 这种结构防止了在形成自对准触点时栅电极的暴露，并且一旦接触开口被填充就会短路。
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3.发明授权Damascene structure having a metal-oxide-metal capacitor associated therewith 有权具有与其相关联的金属氧化物 - 金属电容器的镶嵌结构公开(公告)号：US06680542B1
公开(公告)日：2004-01-20
申请号：US09575214
申请日：2000-05-18
IPC分类号： H01L2348
CPC分类号： H01L28/40 , H01L23/5223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.
摘要翻译： 本发明提供一种包括互连和电容器的半导体器件及其制造方法。 该方法包括通过层间电介质层和位于层间电介质下面的电介质蚀刻停止层形成镶嵌互连结构，其中镶嵌互连结构接触第一互连结构。 该方法还包括通过层间电介质层形成金属氧化物金属（MOM）电容器镶嵌结构，并终止在介电蚀刻停止层上。 在替代实施例中，镶嵌结构可以是双镶嵌结构。 此外，在另一个实施例中，镶嵌互连结构和MOM电容器可以构成较大集成电路的一部分。
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公开(公告)号：US20120295417A1
公开(公告)日：2012-11-22
申请号：US13109567
申请日：2011-05-17
申请人： Thomas N. Adam , Katherina E. Babich , Stephen W. Bedell , Joel P. de Souza , Gerald W. Gibson , Alexander Reznicek , Devendra K. Sadana , Seshadri Subbanna
发明人： Thomas N. Adam , Katherina E. Babich , Stephen W. Bedell , Joel P. de Souza , Gerald W. Gibson , Alexander Reznicek , Devendra K. Sadana , Seshadri Subbanna
IPC分类号： H01L21/20
CPC分类号： H01L29/66628 , H01L21/0237 , H01L21/02524 , H01L21/02639 , H01L29/165 , H01L29/78
摘要： A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed.
摘要翻译： 提供了一种控制外延生长室中不同材料的成核速率（即孵育时间）的方法，其可以有利于高生长速率并且可以与低温生长相容。 通过选择具有给定的天然成核特性的合适的掩蔽材料，通过相对于相同材料膜的单晶生长改变给定材料膜的生长的成核速率，在外延生长室中控制不同材料的成核速率 ，或通过改变掩模层的表面以获得适当的成核特性。 或者，可以通过相对于其后将形成外延半导体材料的其它区域修改半导体衬底的选定区域的表面来实现成核速率控制。
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5.发明授权Structures and methods for low-k or ultra low-k interlayer dielectric pattern transfer 失效低k或超低k层间电介质图案转移的结构和方法公开(公告)号：US07695897B2
公开(公告)日：2010-04-13
申请号：US11429709
申请日：2006-05-08
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.
摘要翻译： 本发明涉及用于形成低k或超低k（即介电常数范围为约1.5至约3.5）层间电介质（ILD）材料的互连图案的改进方法和结构。 具体地说，减小的光刻关键尺寸（CD）（即与目标CD相比）最初用于形成具有增加的厚度的图案化抗蚀剂层，其又允许使用包括下部氮化物掩模层的简单硬掩模层， 用于随后的图案转印的上氧化物掩模层。 接下来通过使用含氧化学物质的第一反应离子蚀刻（RIE）工艺来形成硬掩模叠层，以形成具有与目标CD基本相同的恢复的CD的硬掩模开口。 然后通过使用含氮化学物质的第二RIE方法将ILD材料图案化，以形成与目标CD的互连图案。
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公开(公告)号：US07632690B2
公开(公告)日：2009-12-15
申请号：US11827807
申请日：2007-07-13
IPC分类号： H01L21/00
CPC分类号： H01J37/32935 , H01L21/31138 , H01L21/32139 , H01L21/67069 , H01L21/67253 , Y10T29/41
摘要： A process and apparatus for controlling an etchant gas concentration in an etch chamber. The etchant gas concentration and an inert gas concentration are determined and the latter concentration is used to normalize the etchant gas concentration. The normalized value is compared with a predetermined reference value and the flow of etchant gas into the chamber is controlled in response thereto.
摘要翻译： 用于控制蚀刻室中的蚀刻剂气体浓度的方法和装置。 确定蚀刻剂气体浓度和惰性气体浓度，并将后一浓度用于归一化蚀刻剂气体浓度。 将归一化值与预定的参考值进行比较，并且响应于此而控制蚀刻剂进入腔室的流动。
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公开(公告)号：US6110395A
公开(公告)日：2000-08-29
申请号：US918852
申请日：1997-08-26
CPC分类号： H01J37/32522 , H01J37/32623 , H01J37/3266 , H05H1/46
摘要： The present invention relates to a method and structure for controlling plasma uniformity in plasma processing applications. Electron thermal conductivity parallel and perpendicular to magnetic field lines differs by orders of magnitude for low magnetic fields (on the order of 10 gauss). This property allows the directing of heat flux by controlling the magnetic field configuration independent of ions since the effect of modest magnetic fields upon the transport of ions themselves is minimal. Heat is preferentially conducted along magnetic field lines with electron temperatures on the order of 0.1 to 1 eV/cm being sufficient to drive kilowatt-level heat fluxes across areas typical of plasma processing source dimensions.
摘要翻译： 本发明涉及一种用于控制等离子体处理应用中的等离子体均匀性的方法和结构。 与磁场线平行且垂直的电子热导率对于低磁场（大约10高斯）的数量级不同。 该性质允许通过独立于离子控制磁场构造来引导热通量，因为适度的磁场对离子本身的输送的影响是最小的。 热量优先沿着磁场线传导，电子温度为0.1至1eV / cm左右，足以在等离子体处理源尺寸典型的区域上驱动千瓦级热通量。
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公开(公告)号：US08853856B2
公开(公告)日：2014-10-07
申请号：US12820880
申请日：2010-06-22
IPC分类号： H01L23/48 , B82Y35/00 , H01L21/768 , B82Y40/00 , H01L23/532 , H01L21/66
CPC分类号： H01L23/53276 , B82Y35/00 , B82Y40/00 , H01L21/76808 , H01L21/76835 , H01L21/76885 , H01L22/14 , H01L2221/1031 , H01L2221/1094 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The present disclosure relates to a structure comprising 1. an electrically conductive substrate having carbon nanotubes grown thereon; 2. a cured polymeric fill matrix comprising at least one latent photoacid generator embedded around the carbon nanotubes but allowing tips of the carbon nanotubes to be exposed; 3. a layer of patterned and cured photosensitive dielectric material on the cured polymeric fill matrix, wherein tips of the carbon nanotubes are exposed within the patterns; and 4. an electrically conductive material filled into the interconnect pattern and in contact with the exposed tips of the carbon nanotubes; and to methods of making the structure and using the structure to measure the electrical characteristics of carbon nanotubes.
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9.发明申请公开(公告)号：US20120301980A1
公开(公告)日：2012-11-29
申请号：US13569394
申请日：2012-08-08
IPC分类号： H01L21/66
CPC分类号： H01L23/53276 , B82Y35/00 , B82Y40/00 , H01L21/76808 , H01L21/76835 , H01L21/76885 , H01L22/14 , H01L2221/1031 , H01L2221/1094 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The present disclosure relates to a structure comprising 1. an electrically conductive substrate having carbon nanotubes grown thereon; 2. a cured polymeric fill matrix comprising at least one latent photoacid generator embedded around the carbon nanotubes but allowing tips of the carbon nantotubes to be exposed; 3. a layer of patterned and cured photosensitive dielectric material on the cured polymeric fill matrix, wherein tips of the carbon nantobues are exposed within the patterns; and 4. an electrically conductive material filled into the interconnect pattern and in contact with the exposed tips of the carbon nanotubes; and to methods of making the structure and using the structure to measure the electrical characteristics of carbon nanotubes.
摘要翻译： 本公开涉及一种结构，其包括：其上生长有碳纳米管的导电基材; 2.一种固化的聚合物填充基质，其包含嵌入碳纳米管周围的至少一个潜在光致酸发生剂，但允许碳纳米管的尖端暴露; 在固化的聚合物填充基质上的一层图案化和固化的光敏电介质材料，其中碳纳米管的尖端在图案内暴露; 4.一种填充到互连图案中并与碳纳米管的暴露尖端接触的导电材料; 以及制造该结构并使用该结构来测量碳纳米管的电特性的方法。
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公开(公告)号：US07261745B2
公开(公告)日：2007-08-28
申请号：US10675572
申请日：2003-09-30
CPC分类号： H01J37/32935 , H01L21/31138 , H01L21/32139 , H01L21/67069 , H01L21/67253 , Y10T29/41
摘要： A process and apparatus for controlling an etchant gas concentration in an etch chamber. The etchant gas concentration and an inert gas concentration are determined and the latter concentration is used to normalize the etchant gas concentration. The normalized value is compared with a predetermined reference value and the flow of etchant gas into the chamber is controlled in response thereto.
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