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    Processor instruction used to perform a matrix test to generate a memory-related trap
    1.
    发明授权
    Processor instruction used to perform a matrix test to generate a memory-related trap 有权
    处理器指令用于执行矩阵测试以生成与存储器相关的陷阱

    公开(公告)号：US08108628B2

    公开(公告)日：2012-01-31

    申请号：US12658669

    申请日：2010-02-12

    申请人： Jack H. Choquette ,  Gil Tene ,  Michael A. Wolf

    发明人： Jack H. Choquette ,  Gil Tene ,  Michael A. Wolf

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0253 ,  G06F9/3004 ,  G06F9/3861 ,  G06F11/2236

    摘要： Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test. The second set of one or more bits is used in the determination of whether to perform the trap; and the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits.

    摘要翻译： 指令执行包括获取包括识别指令的一个或多个比特的第一组的指令，以及与第一地址值相关联的一个或多个比特的第二组。 它还包括执行指令以确定是否执行陷阱，其中执行指令包括从多个测试中选择至少一个用于确定是否执行陷阱并进行至少一个测试的测试。 在确定是否执行陷阱时使用第二组一个或多个比特; 并且所述多个测试包括矩阵测试，所述矩阵测试确定由所述第一地址值指示的存储的数据值是否从多个管理存储器类型中的一个转移到所述多个管理存储器类型中的另一个，并产生陷阱 在数据值被确定为从多个托管存储器类型之一转移到多个托管存储器类型中的另一个的情况下，其中矩阵测试基于与垃圾收集相关联的矩阵和位于 使用一个或多个比特的第一组中的至少一些以及一个或多个比特的第二组中的至少一些。

    ACCELERATED CLASS CHECK
    2.
    发明申请
    ACCELERATED CLASS CHECK 有权
    加速类检查

    公开(公告)号：US20110321064A1

    公开(公告)日：2011-12-29

    申请号：US13227111

    申请日：2011-09-07

    申请人： Gil Tene ,  Cliff N. Click, JR. ,  Murali Sundaresan ,  Michael A. Wolf

    发明人： Gil Tene ,  Cliff N. Click, JR. ,  Murali Sundaresan ,  Michael A. Wolf

    IPC分类号： G06F9/42

    CPC分类号： G06F9/4428 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/4488 ,  G06F9/449 ,  G06F9/455

    摘要： Handling a virtual method call includes extracting, from a pointer to an object, an identifier associated with the class of the object, the pointer to the object being associated with the virtual method call, and the identifier being embedded within the pointer; using the identifier to obtain a virtual method table, including locating a first entry in a class identifier table mapping a plurality of class identifiers to a corresponding plurality of class data, the first entry being associated with the identifier and comprising the virtual method table or a pointer used to obtain the virtual method table; locating a second entry in the virtual method table, the second entry being associated with the virtual method call; and jumping to an address associated with the second entry to execute code at the address.

    摘要翻译： 处理虚拟方法调用包括从对象的指针提取与对象的类相关联的标识符，与虚拟方法调用相关联的对象的指针，以及嵌入在指针内的标识符; 使用所述标识符来获得虚拟方法表，包括将映射多个类标识符的类标识符表中的第一条目定位到对应的多个类数据，所述第一条目与所述标识符相关联，并且包括所述虚方法表或 指针用于获取虚拟方法表; 在虚拟方法表中定位第二条目，第二条目与虚拟方法调用相关联; 并跳转到与第二条目相关联的地址，以在该地址处执行代码。

    Processor instruction used to determine whether to perform a memory-related trap
    4.
    发明申请
    Processor instruction used to determine whether to perform a memory-related trap 有权
    处理器指令用于确定是否执行内存相关的陷阱

    公开(公告)号：US20100153689A1

    公开(公告)日：2010-06-17

    申请号：US12658669

    申请日：2010-02-12

    申请人： Jack Choquette ,  Gil Tene ,  Michael A. Wolf

    发明人： Jack Choquette ,  Gil Tene ,  Michael A. Wolf

    IPC分类号： G06F9/38 ,  G06F12/10

    CPC分类号： G06F12/0253 ,  G06F9/3004 ,  G06F9/3861 ,  G06F11/2236

    摘要： Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test. The second set of one or more bits is used in the determination of whether to perform the trap; and the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits.

    摘要翻译： 指令执行包括获取包括识别指令的一个或多个比特的第一组的指令，以及与第一地址值相关联的一个或多个比特的第二组。 它还包括执行指令以确定是否执行陷阱，其中执行指令包括从多个测试中选择至少一个用于确定是否执行陷阱并进行至少一个测试的测试。 在确定是否执行陷阱时使用第二组一个或多个比特; 并且所述多个测试包括矩阵测试，所述矩阵测试确定由所述第一地址值指示的存储的数据值是否从多个管理存储器类型中的一个转移到所述多个管理存储器类型中的另一个，并产生陷阱 在数据值被确定为从多个托管存储器类型之一转移到多个托管存储器类型中的另一个的情况下，其中矩阵测试基于与垃圾收集相关联的矩阵和位于 使用一个或多个比特的第一组中的至少一些以及一个或多个比特的第二组中的至少一些。

    Segmented virtual machine transport mechanism
    5.
    发明申请
    Segmented virtual machine transport mechanism 有权
    分段虚拟机传输机制

    公开(公告)号：US20090178039A1

    公开(公告)日：2009-07-09

    申请号：US12315854

    申请日：2008-12-05

    申请人： Gil Tene ,  Michael A. Wolf ,  Anirban Sengupta ,  Sivakumar Annamalai ,  Adrian Sun

    发明人： Gil Tene ,  Michael A. Wolf ,  Anirban Sengupta ,  Sivakumar Annamalai ,  Adrian Sun

    IPC分类号： G06F9/455

    CPC分类号： G06F9/544 ,  G06F9/45533

    摘要： Providing data to an application running on a segmented virtual machine (VM) is disclosed. Providing data includes opening an interface between the segmented VM and an external data source, transferring data from the external data source to an interface buffer, transferring a first selected amount of data from the interface buffer to a shell VM buffer, transferring a second selected amount of data from the shell VM buffer to a core VM buffer, and providing portions of the data from the core VM buffer to the application in response to read requests from the application.

    摘要翻译： 公开了向分段虚拟机（VM）上运行的应用提供数据。 提供数据包括打开分段的VM和外部数据源之间的接口，将数据从外部数据源传送到接口缓冲器，将第一选定数量的数据从接口缓冲器传送到壳VM缓冲器，传送第二选定量 的数据从shell VM缓冲区提供到核心VM缓冲区，以及响应于来自应用程序的读取请求，将数据从核心VM缓冲区提供给应用程序。

    Memory management
    7.
    发明授权
    Memory management 有权
    内存管理

    公开(公告)号：US07257685B2

    公开(公告)日：2007-08-14

    申请号：US11503388

    申请日：2006-08-11

    申请人： Gil Tene ,  Cliff N. Click ,  Michael A. Wolf ,  Ivan Posva

    发明人： Gil Tene ,  Cliff N. Click ,  Michael A. Wolf ,  Ivan Posva

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0253 ,  G06F9/5016

    摘要： Improving performance of a computer program is disclosed. A first set of escape data is gathered. A first compiled program is provided using the first set of escape data. A second set of escape data is gathered based on the first compiled program. A second compiled program is provided using the second set of escape data. The second compiled program is more optimized than the first compiled program.

    摘要翻译： 公开了改进计算机程序的性能。 收集第一组转义数据。 使用第一组转义数据提供第一个编译程序。 基于第一个编译程序收集第二组转义数据。 使用第二组转义数据提供第二个编译程序。 第二个编译程序比第一个编译程序更优化。

    System and method for concurrent compacting self pacing garbage collection using loaded value and access barriers
    8.
    发明申请
    System and method for concurrent compacting self pacing garbage collection using loaded value and access barriers 有权
    使用负载值和访问障碍并发压缩自动起搏垃圾收集的系统和方法

    公开(公告)号：US20060155791A1

    公开(公告)日：2006-07-13

    申请号：US11031015

    申请日：2005-01-07

    申请人： Gil Tene ,  Michael Wolf

    发明人： Gil Tene ,  Michael Wolf

    IPC分类号： G06F17/30

    CPC分类号： G06F12/0269 ,  Y10S707/99953 ,  Y10S707/99957

    摘要： A method, system, and computer program product for managing a heap of memory allocated to a program being executed on a data processing system is disclosed. A limited amount of memory is allocated to a program being executed by a mutator on a data processing system. The memory comprises memory objects. The disclosed method identifies memory objects, which are allocated to the program but are not referenced anymore. These dead memory objects are freed and made available for further allocation in the program. The memory objects that are still referenced are organized in compact contiguous blocks. Thus, the disclosed method recycles memory allocated to the program. The disclosed method is executed iteratively and concurrently with the execution of the program. The disclosed method does not interfere with program execution. Amount of memory required is specified before the commencement of the disclosed method and the same amount is freed without any surplus.

    摘要翻译： 公开了一种用于管理分配给正在数据处理系统上执行的程序的存储器堆的方法，系统和计算机程序产品。 将有限量的存储器分配给由数据处理系统上的变焦器执行的程序。 存储器包括存储器对象。 所公开的方法标识被分配给程序但不再被引用的存储器对象。 这些死记忆物体被释放并可用于程序中的进一步分配。 仍然引用的内存对象被组织在紧凑的连续块中。 因此，所公开的方法回收分配给程序的存储器。 所公开的方法与程序的执行迭代地同时执行。 所公开的方法不干扰程序执行。 所需的记忆量在所公开方法生效之前规定，相同的金额在没有任何盈余的情况下被释放。

    Detecting and recording atomic execution
    9.
    发明授权
    Detecting and recording atomic execution 有权

    公开(公告)号：US09928072B1

    公开(公告)日：2018-03-27

    申请号：US12387478

    申请日：2009-05-01

    申请人： Gil Tene ,  Michael A. Wolf ,  Cliff N. Click, Jr.

    发明人： Gil Tene ,  Michael A. Wolf ,  Cliff N. Click, Jr.

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F11/36

    CPC分类号： G06F9/3842 ,  G06F9/30 ,  G06F11/3636

    摘要： A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units is not programmatically specified to be executed atomically; detect an atomicity terminating event during atomic execution of the plurality of instruction units, wherein the atomicity terminating event is triggered by a memory access by another processor; and establish an incidentally atomic sequence of instruction units based at least in part on detection of the atomicity terminating event, wherein the incidentally atomic sequence of instruction units correspond to a sequence of instruction units in the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.