公开(公告)号：US08916421B2

公开(公告)日：2014-12-23

申请号：US13222148

申请日：2011-08-31

申请人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

发明人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

IPC分类号： H01L21/70 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L21/486 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00

摘要： A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.

摘要翻译： 提供了一种通过通孔预先形成和放置的​​半导体器件封装以及用于制造这种封装的工艺。 一个或多个信号管道耦合到引线框架，引线框架随后嵌入在封装的半导体器件封装中。 信号管道的自由端被暴露，而另一端保持联接到引线框架。 然后，信号导管用作通过封装通孔，在封装的底部和顶部与引线之间的互连或接触之间提供信号承载通路。

公开(公告)号：US08327126B2

公开(公告)日：2012-12-04

申请号：US12197357

申请日：2008-08-25

申请人： Robert H. Bell, Jr. ,  Louis Bennie Capps, Jr. ,  Thomas Edward Cook ,  Glenn G. Daves ,  Ronald Edward Newhart ,  Michael A. Paolini ,  Michael Jay Shapiro

发明人： Robert H. Bell, Jr. ,  Louis Bennie Capps, Jr. ,  Thomas Edward Cook ,  Glenn G. Daves ,  Ronald Edward Newhart ,  Michael A. Paolini ,  Michael Jay Shapiro

IPC分类号： G06F9/00 ,  G06F9/22 ,  G06F9/24 ,  G06F9/46

CPC分类号： G06F15/7871

摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

摘要翻译： 处理器具有多个核心，每个核心具有相关功能以支持处理器操作。 通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。 例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。 作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。

公开(公告)号：US06878608B2

公开(公告)日：2005-04-12

申请号：US09870531

申请日：2001-05-31

申请人： Peter J. Brofman ,  Glenn G. Daves ,  Sudipta K. Ray ,  Herbert I. Stoller

发明人： Peter J. Brofman ,  Glenn G. Daves ,  Sudipta K. Ray ,  Herbert I. Stoller

IPC分类号： H01L21/48 ,  H01L21/68 ,  H01L21/46 ,  H01L21/30 ,  H01L21/302 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/6835 ,  H01L21/486 ,  H01L24/16 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2224/16237 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

摘要： A silicon based package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Forming via holes which extend through the UTSW, forming metallization in the via holes which extends through the UTSW, making electrical contact to the interconnection structure on the first surface. Then bond the metallization in the via holes to pads of a carrier.

摘要翻译： 基于硅的封装（SBP）从用作SBP的基底的厚晶片开始形成，所述基板由具有平坦的第一表面和反面的硅组成。 然后在第一表面上形成包括多层导体图案的互连结构。 在SBP和晶片保持器之间形成临时结合，晶片保持器是刚性结构。 将晶片细化至所需厚度，以形成SBP的超薄硅片（UTSW）。 形成穿过UTSW的孔，在穿过UTSW的通孔中形成金属化，与第一表面上的互连结构电接触。 然后将通孔中的金属化物接合到载体的焊盘。

公开(公告)号：US06762489B2

公开(公告)日：2004-07-13

申请号：US09989666

申请日：2001-11-20

申请人： Glenn G. Daves ,  Jason Frankel ,  William F. Shutler ,  Anthony Wayne Sigler ,  Herbert I. Stoller ,  John Vetrero ,  Cathy Ann Zadany

发明人： Glenn G. Daves ,  Jason Frankel ,  William F. Shutler ,  Anthony Wayne Sigler ,  Herbert I. Stoller ,  John Vetrero ,  Cathy Ann Zadany

IPC分类号： H01L2348

CPC分类号： H01L24/17 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H05K1/0289 ,  H05K1/112

摘要： A jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module is disclosed. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.

摘要翻译： 公开了一种用于将布线连接从第一网格中的点转换到芯片载体模块中的第二网格中的相应点的慢跑结构。 在示例性实施例中，该结构包括耦合到第一格栅的第一平移层，第一平移层沿x轴方向平移第一格栅。 第二平移层耦合到第一平移层，第二平移层用于在y轴方向上从第一栅格平移所述布线连接，y轴方向与x轴方向正交。 第二平移层还耦合到第二栅极。

公开(公告)号：US08645673B2

公开(公告)日：2014-02-04

申请号：US13613936

申请日：2012-09-13

申请人： Robert H. Bell, Jr. ,  Louis Bennie Capps, Jr. ,  Thomas Edward Cook ,  Glenn G. Daves ,  Ronald Edward Newhart ,  Michael A. Paolini ,  Michael Jay Shapiro

发明人： Robert H. Bell, Jr. ,  Louis Bennie Capps, Jr. ,  Thomas Edward Cook ,  Glenn G. Daves ,  Ronald Edward Newhart ,  Michael A. Paolini ,  Michael Jay Shapiro

IPC分类号： G06F9/00 ,  G06F9/06 ,  G06F9/24

CPC分类号： G06F15/7871

摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

摘要翻译： 处理器具有多个核心，每个核心具有相关功能以支持处理器操作。 通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。 例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。 作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。

公开(公告)号：US20130049218A1

公开(公告)日：2013-02-28

申请号：US13222150

申请日：2011-08-31

申请人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

发明人： Zhiwei Gong ,  Navjot Chhabra ,  Glenn G. Daves ,  Scott M. Hayes

IPC分类号： H01L21/77 ,  H01L21/56 ,  H01L23/48

CPC分类号： H01L24/19 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4602 ,  H05K2203/0733 ,  H01L2924/00

摘要： A method for forming signal conduits before encapsulation for incorporation as through vias in a semiconductor device package is provided. One or more signal conduits are formed through photolithography and metal deposition on a metal film or substrate. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die and other parts of the package. The ends of the signal conduits are exposed and the signal conduits can then be used as through vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package, and electrical contacts of the semiconductor die. Using this method, signal conduits can be provided in a variety of geometric placings in the semiconductor device package. A semiconductor device package including the signal conduits made from the above method is also provided.

摘要翻译： 提供了一种用于在封装之前形成信号导管以在半导体器件封装中通过通孔并入的方法。 通过光刻和金属沉积在金属膜或衬底上形成一个或多个信号导管。 在除去光致抗蚀材料之后，通过封装信号导管以及任何半导体管芯和封装的其它部分来构建半导体器件封装。 信号管道的端部被暴露，然后可以将信号导管用作通孔，在封装的底部和顶部上的互连或触点之间提供信号承载通路，以及半导体管芯的电触头。 使用该方法，信号导管可以以半导体器件封装中的各种几何布置提供。 还提供了包括由上述方法制成的信号导管的半导体器件封装。

公开(公告)号：US20080261350A1

公开(公告)日：2008-10-23

申请号：US12146798

申请日：2008-06-26

申请人： Glenn G. Daves ,  David L. Edwards ,  Mukta G. Farooq ,  Frank L. Pompeo

发明人： Glenn G. Daves ,  David L. Edwards ,  Mukta G. Farooq ,  Frank L. Pompeo

IPC分类号： H05K3/36 ,  H01L21/00 ,  B23K31/02

CPC分类号： B23K3/0638 ,  B23K2101/40 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H05K3/301 ,  H05K3/303 ,  H05K3/305 ,  H05K2201/0209 ,  H05K2201/09909 ,  H05K2201/10234 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2201/2018 ,  H05K2201/2036 ,  Y02P70/613 ,  Y10T29/49144 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.

摘要翻译： 一种用于组装的方法，并且所得到的电子模块包括使用第一焊料互连阵列将芯片附接到衬底，并且使用第二焊料互连阵列将衬底附接到衬底，第二焊料互连阵列可以是单熔体或双 - 熔融焊料阵列。 第二焊料互连阵列完全位于限定在板和衬底之间的空间内。 在该空间内设有抗蠕变结构，用于维持限定的空间并优化第二焊料互连阵列的完整性。 抗蠕变结构可以包括底部填充材料，球，支架，框架，套环或其组合。 其中抗蠕变结构是底部填充材料，在将基板完全用底部填充材料完全封装第二互连阵列之前，或者在具有底部填充材料的不连续位置部分地封装第二焊料互连阵列之前，衬底附着到板上是至关重要的。

公开(公告)号：US06541365B2

公开(公告)日：2003-04-01

申请号：US09992360

申请日：2001-11-14

申请人： David L. Edwards ,  Norman J. Dauerer ,  Glenn G. Daves

发明人： David L. Edwards ,  Norman J. Dauerer ,  Glenn G. Daves

IPC分类号： H01L2144

CPC分类号： H01L21/6835 ,  G01R1/0408 ,  G01R1/0466 ,  G01R1/0483 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/162 ,  H05K2203/176 ,  Y02P70/613 ,  H01L2924/00

摘要： The present invention relates generally to a new structure and a method for reducing the cost of producing known good die (KGD). More particularly, the invention encompasses a structure and a method that uses a substrate having solder wettable pads, a chip with attached solder balls, and a thin non-conductive interposer that is assembled between the chip and the substrate. The interposer reduces the cross section of the solder connections from the chip to the substrate where the solder passes through (the holes in) the interposer. This reduced cross-sectional area of the solder connection creates a weak point which allows the chip to be easily sheared off of the substrate after a burn-in and test process. The preferred chips for this invention are flip chips.

公开(公告)号：US06292369B1

公开(公告)日：2001-09-18

申请号：US09633788

申请日：2000-08-07

申请人： Glenn G. Daves ,  David L. Edwards

发明人： Glenn G. Daves ,  David L. Edwards

IPC分类号： H05K720

CPC分类号： H01L21/50 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15312 ,  H01L2924/16152 ,  Y10T29/4913

摘要： Integrated circuit chip packaging modules and lid structures having improved heat dissipation performance are characterized by a customized lid understructure which enables a reduction in the amount of compliant thermally conductive material in the primary heat dissipation path. The lid structures and modules are made by processes wherein the lid understructure is customized for the chip(s) to be housed. The customization is achieved by the use of shims and a deformable lid understructure.

摘要翻译： 具有改善的散热性能的集成电路芯片封装模块和盖结构的特征在于定制的盖子下部结构，其能够减少主散热路径中的柔性导热材料的量。 盖结构和模块通过以下方法制成：其中盖子下部结构被定制成要被容纳的芯片。 定制是通过使用垫片和可变形的盖子结构来实现的。

公开(公告)号：US09059144B2

公开(公告)日：2015-06-16

申请号：US13403458

申请日：2012-02-23

申请人： Leo M. Higgins, III ,  Burton J. Carpenter ,  Glenn G. Daves

发明人： Leo M. Higgins, III ,  Burton J. Carpenter ,  Glenn G. Daves

IPC分类号： H01L23/34 ,  H01L23/433 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L23/4334 ,  H01L21/566 ,  H01L23/3128 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method for forming a molded die assembly includes attaching a first major surface of a semiconductor die onto a package substrate; attaching a heat spreader to a second major surface of the semiconductor die, wherein the second major surface is opposite the first major surface, and wherein the semiconductor die, package substrate, and heat spreader form a die assembly; conforming a die release film to a transfer mold; closing the transfer mold around the die assembly such that the die release film is compressed against the heat spreader and a cavity is formed around the die assembly; transferring a thermoset material into the cavity; and releasing the die assembly from the die release film and the transfer mold.

摘要翻译： 一种用于形成模制模具组件的方法包括将半导体管芯的第一主表面附接到封装衬底上; 将散热器附接到所述半导体管芯的第二主表面，其中所述第二主表面与所述第一主表面相对，并且其中所述半导体管芯，封装衬底和散热器形成管芯组件; 将脱模膜贴合到转移模具上; 关闭模具组件周围的转移模具，使得脱模膜压靠散热器并且在模具组件周围形成空腔; 将热固性材料转移到空腔中; 以及从模具脱模膜和转移模具中释放模具组件。