公开(公告)号：US20250070781A1

公开(公告)日：2025-02-27

申请号：US18455669

申请日：2023-08-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Mei Yu Soh

IPC: H03K19/003 ,  H03K17/0412

Abstract: Disclosed circuit structure embodiments include an enhancement mode transistor and a turn-off slew rate controller for automatically adding drain-source capacitance to the transistors when the transistor is transitioning to an off state. The added drain-source capacitance slows the turn-off slew rate (dV/dt_off) of the transistor without also increasing the turn-off energy loss (E_off). In some embodiments, the slew rate controller includes: sensors connected to the drain region for sensing both the drain voltage and the slew rate, respectively; a logic circuit for generating and outputting an enable signal based on output voltages from the sensors; and a capacitance adder for adding to the drain-source capacitance only when the logic value of the enable signal indicates that the drain voltage is at or above a predetermined positive drain voltage level and the slew rate is positive.

公开(公告)号：US12237407B2

公开(公告)日：2025-02-25

申请号：US17978633

申请日：2022-11-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Rajendran Krishnasamy ,  Vvss Satyasuresh Choppalli ,  Vibhor Jain ,  Robert J. Gauthier, Jr.

IPC: H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.

公开(公告)号：US20250056783A1

公开(公告)日：2025-02-13

申请号：US18448467

申请日：2023-08-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Meixiong Zhao ,  Hongliang Shen ,  Randy William Mann

IPC: H10B10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: Disclosed semiconductor structures include semiconductor fin(s), each extending from a semiconductor substrate and having opposing sidewalls. Each fin has a lower portion and an upper portion above the lower portion. The lower portion has a base proximal to the semiconductor substrate and divots within the opposing sidewalls at the base. An isolation region is on the semiconductor substrate adjacent to the opposing sidewalls of each fin (e.g., including within the divots). The upper portion of each fin extends above the level of the top surface of the isolation region and can be incorporated into a single-fin or multi-fin fin-type device (e.g., a fin-type field effect transistor (FINFET)). In some embodiments, multiple single-fin and/or multi-fin FINFETs incorporating the upper portions of such fins can be incorporated into a memory cell, such as a static random access memory (SRAM) cell. Also disclosed herein are associated method embodiments.

公开(公告)号：US20250054908A1

公开(公告)日：2025-02-13

申请号：US18232876

申请日：2023-08-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Brett Cucci ,  Ramsey Hazbun ,  Richard Rassel ,  Zhong-Xiang He ,  Patrick Mitchell

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48

Abstract: Structures including a compound semiconductor layer stack and methods of forming such structures. The structure comprises a device region on a substrate. The device region includes a first section of a layer stack that has a plurality of semiconductor layers, and each semiconductor layer comprises a compound semiconductor material. The structure further comprises an isolation structure disposed about the section of the layer stack, and a device in the device region. The isolation structure penetrates through the layer stack to the substrate.

公开(公告)号：US12222376B2

公开(公告)日：2025-02-11

申请号：US17815961

申请日：2022-07-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Indranil Som ,  Vaibhav Anantrai Ruparelia ,  Kuppireddy Vasudeva Reddy

IPC: G01R19/04

Abstract: Embodiments of the disclosure provide a peak voltage detection circuit with reduced charge loss. A circuit structure of the disclosure includes a peak voltage detector having a first input node coupled to an input line and a second input node coupled to a first electrically actuated switch. The peak voltage detector coupling the first input node and the second input node to an output node, and a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor. The first electrically actuated switch couples the capacitor to the second input node of the peak voltage detector. The input line is coupled to a control node of the first electrically actuated switch and a control node of the second electrically actuated switch.

公开(公告)号：US12222257B2

公开(公告)日：2025-02-11

申请号：US17657175

申请日：2022-03-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hanyi Ding ,  Aidong Yan ,  Rongtao Cao

IPC: G01M11/00 ,  G02B6/42

Abstract: A structure for testing a photodiode in a PIC using a grating coupler in optical communication with an optical terminal in a different location of the photodiode from another optical terminal used during operation of the PIC. The photodiode includes an operational optical terminal and a test optical terminal with the test optical terminal in a different location than the operational optical terminal. An optical component is in optical communication with the operational optical terminal of the photodiode and is used during operation of the photodiode and the PIC. A grating coupler is in optical communication with the test optical terminal of the photodiode for testing purposes.

公开(公告)号：US20250035840A1

公开(公告)日：2025-01-30

申请号：US18225709

申请日：2023-07-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Kenneth Giewont ,  Takako Hirokawa

IPC: G02B6/122 ,  G02B6/13

Abstract: Structures for a photonics chip that include a photonic component and methods of forming such structures. The structure may comprise a photodetector on a substrate and a waveguide core. The photodetector includes a light-absorbing layer having a longitudinal axis, a first sidewall, and a second sidewall adjoined to the first sidewall at an interior angle. The first sidewall is slanted relative to the longitudinal axis, and the second sidewall is oriented transverse to the longitudinal axis. The waveguide core includes a tapered section adjacent to the first sidewall and the second sidewall of the light-absorbing layer.

公开(公告)号：US12204146B2

公开(公告)日：2025-01-21

申请号：US17869065

申请日：2022-07-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/125 ,  G02B6/122 ,  G02B6/136 ,  G02B6/12

Abstract: Structures for a waveguide crossing and methods of forming such structures. The structure comprises a first waveguide core including a first section, a second section, and a first longitudinal axis. The first section and the second section are aligned along the first longitudinal axis, the first section is terminated by a first end, the second section is terminated by a second end, and the first end of the first section is longitudinally spaced from the second end of the second section by a gap. The structure further comprises a second waveguide core having a second longitudinal axis angled relative to the first longitudinal axis. The second longitudinal axis of the second waveguide core crosses the first longitudinal axis of the first waveguide core within the gap.

公开(公告)号：US20250023565A1

公开(公告)日：2025-01-16

申请号：US18350294

申请日：2023-07-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu

IPC: H03K19/0185

Abstract: Disclosed structures include a single-stage and a multi-stage voltage level shifter. Each structure includes multiple transistors, which are optionally all symmetric low-voltage transistors, and the structures are configured to avoid operation outside the safe operating area (SOA) of such transistors. The single-stage voltage level shifter and the first stage of the multi-stage voltage level shifter can be essentially identical. In operation, input voltage pulses (including an input voltage pulse transitioning between a first positive voltage (V1) equal to the voltage rating of the transistors and ground) can be received at source nodes of N-type transistors and, in response, output voltage pulses (including an intermediate output voltage pulse transitioning between V1 and a second positive voltage (V2) that is higher than (e.g., double) V1 and an output voltage pulse that transitions between ground and V2) can be output.

公开(公告)号：US12199147B2

公开(公告)日：2025-01-14

申请号：US17734135

申请日：2022-05-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vvss Satyasuresh Choppalli ,  Anupam Dutta ,  Aaron Lee Vallett

IPC: H01L29/10 ,  H01L21/74

Abstract: The present disclosure relates to a semiconductor device including a substrate, a first region disposed in the substrate, a terminal region disposed in the first region, a body contact region disposed in the first region and spaced apart from the terminal region, a dielectric layer disposed on the substrate over the first region between the terminal region and the body contact region, an electrically conductive layer disposed on the dielectric layer, and a continuous metallic layer disposed on the electrically conductive layer and extending to the body contact region, the continuous metallic layer disposed on the body contact region and in physical contact with a top and side portions of the electrically conductive layer. The semiconductor device may additionally include a body contact interconnect disposed on a portion of the continuous metallic layer over the electrically conductive layer.