摘要:
Multi-metallization level semiconductor devices are formed without degrading a low k dielectric gap fill material due to multiple pre-metallization degassing/outgassing heat treatments. Degradation of the low k material is substantially reduced or eliminated by employing time intervals for heat treatment which are not longer than the longest metal deposition step and temperatures below that which the dielectric material decomposes.
摘要:
A fabrication method reduces the amount of discoloration on interlevel dielectric layers due to anti-reflective coatings (ARC). The invention utilizes a barrier layer, such as, silicon nitride (SiN) that prevents the anti-reflective coating from contacting the interlevel dielectric layer (ILD0). The anti-reflective coating can be silicon oxynitride (SiON) deposited by LPCVD or PECVD.
摘要:
A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.
摘要:
In a preferred embodiment, there is disclosed a method of forming a tungsten plug at the via level. A metal line is formed in a top portion of a first insulating layer. A second insulating layer is formed on the first insulating layer and over an exposed surface of the metal line. An etching process is applied to a region of the second insulating layer formed over the exposed surface of the metal line to create a contact hole within the region. The metal line is exposed at the region. A tungsten nitride thin film is deposited over the second insulating layer and the exposed metal line. A blanket tungsten thin film is deposited to fill the contact hole and to form a planar layer successively to the depositing of the tungsten nitride thin film. The tungsten nitride thin film and the blanket tungsten thin film are chemically mechanically polished until the upper surface of the second insulating layer is exposed.
摘要:
A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.
摘要:
A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
摘要:
A method of reducing contact size in an integrated circuit includes providing an insulating layer over a semiconductor substrate including a plurality of gate structures, creating an aperture extending through the insulating layer and having side walls, providing a spacer on the side walls of the aperture, and providing a contact in the aperture. The lateral sides of the contact abut the spacer. A contact structure is also disclosed in which a spacer separates a contact from a gate structure to avoid charge gain or loss between the contact and gate structure.
摘要:
A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
摘要:
A method of depositing metal silicide onto a semiconductor substrate includes a step of depositing, by a CVD process, a first metal silicide layer with silane gas onto the semiconductor substrate. The method also includes a step of thermally treating and chemically cleaning the semiconductor substrate. The method further includes a step of depositing, by the CVD process, a second metal silicide layer with silane gas onto the semiconductor substrate. By this method, cracks in the metal silicide formed on the semiconductor substrate are minimized.
摘要:
Borderless submicron vias are formed between patterned metal layers gap filled with a high density plasma oxide. Heat treatment is conducted after chemical vapor deposition of the high density plasma oxide to substantially increase the grain size of the patterned metal layers, thereby improving electromigration resistance.