DIGITAL CLOCK REGENERATOR
    1.
    发明申请
    DIGITAL CLOCK REGENERATOR 有权
    数字时钟再生器

    公开(公告)号:US20120293224A1

    公开(公告)日:2012-11-22

    申请号:US13576496

    申请日:2010-02-17

    Inventor: Gunnar Forsberg

    CPC classification number: H04L7/033 G06F1/08

    Abstract: A sampling unit (110) receives an input clock signal (CLKin) having a varying period time, and samples the input clock signal (CLKin) based on a sampling clock signal (CLKsmpl) that has a frequency being substantially higher than an average frequency of the input clock signal (CLKin). The sampling unit (110) produces a respective period length value (PL) for each period of the input clock signal (CLKin). An averaging unit (120) receives a number of period length values (PL) from the sampling unit (110), and based thereon produces an average period length value (PLavg) representing an average period time for the input clock signal (CLKin) over an averaging interval including a number of periods equivalent to said number of period length values (PL). An output unit (151) produces a stabilized output clock signal (CLKout) based on the average period length value (PLavg) and the sampling clock signal (CLKsmpl).

    Abstract translation: 采样单元(110)接收具有变化周期时间的输入时钟信号(CLKin),并且基于采样时钟信号(CLKsmpl)对输入时钟信号(CLKin)进行采样,该采样时钟信号(CLKsmpl)的频率明显高于 输入时钟信号(CLKin)。 采样单元(110)针对输入时钟信号(CLKin)的每个周期产生相应的周期长度值(PL)。 平均单元(120)从采样单元(110)接收多个周期长度值(PL),并且基于此产生表示输入时钟信号(CLKin)的平均周期时间的平均周期长度值(PLavg) 平均间隔,其包括与所述周期长度值(PL)的数量相当的周期数。 输出单元(151)基于平均周期长度值(PLavg)和采样时钟信号(CLKsmpl)产生稳定的输出时钟信号(CLKout)。

    Method for conveying management information
    2.
    发明申请
    Method for conveying management information 有权
    传送管理信息的方法

    公开(公告)号:US20070077065A1

    公开(公告)日:2007-04-05

    申请号:US10557022

    申请日:2004-05-11

    Abstract: The invention relates to a method for conveying management information in a WDM system from a number of wavelength converters to a central management unit, wherein a management information signal is superimposed on the WDM signal from the respective wavelength converter. A fraction of the optical signal in the common optical transmission line is tapped off to a detector and the different management information signals are recovered by a receiver unit which is connected to the detector. The invention also relates to a WDM system and a pluggable WDM wavelength converter.

    Abstract translation: 本发明涉及一种用于将WDM系统中的管理信息从多个波长转换器传送到中央管理单元的方法,其中管理信息信号叠加在来自相应波长转换器的WDM信号上。 公共光传输线中的光信号的一部分被分接到检测器,并且不同的管理信息信号由连接到检测器的接收器单元恢复。 本发明还涉及WDM系统和可插拔WDM波长转换器。

    System with feedback controlled optical amplifiers
    4.
    发明授权
    System with feedback controlled optical amplifiers 有权
    具有反馈控制光放大器的系统

    公开(公告)号:US06215583B1

    公开(公告)日:2001-04-10

    申请号:US09254712

    申请日:1999-11-19

    CPC classification number: H04B10/296 H01S3/1301 H04B10/294

    Abstract: The present invention relates to an optical system with an optical amplifier having at least one input and output, a control circuit for controlling the output power of the amplifier with the aid of an output process demand signal (PD) from a control means. The control circuit comprises control means, a detector block and a means for tapping off light from an input or an output of the optical amplifier to the detector block. According to the invention, at least one check signal (A) is disposed to be sent in at least one check signal channel which passes through the optical amplifier. The detector block is configured to measure the amplitude of the control signal(s).

    Abstract translation: 本发明涉及具有至少一个输入和输出的具有光学放大器的光学系统,一个控制电路,借助于来自控制装置的输出处理要求信号(PD)来控制放大器的输出功率。 控制电路包括控制装置,检测器块和用于将光从光放大器的输入或输出抽出到检测器块的装置。 根据本发明,至少一个检查信号(A)被布置成在通过光放大器的至少一个检查信号通道中发送。 检测器块被配置为测量控制信号的幅度。

    Arrangements relating to light emitting devices
    5.
    发明授权
    Arrangements relating to light emitting devices 失效
    有关发光器件的安排

    公开(公告)号:US6049175A

    公开(公告)日:2000-04-11

    申请号:US969850

    申请日:1997-11-14

    Inventor: Gunnar Forsberg

    CPC classification number: H04B10/564 H01S5/04 H04B10/502 H01S5/0427

    Abstract: A light transmitting arrangement includes a light emitting device, for example a light emitting diode and an arrangement for peaking the current through the light emitting device upon switching on and/or off. The peaking arrangement includes a peaking network which is arranged in parallel with a light emitting device and which is a passive network.

    Abstract translation: 光发射装置包括发光器件,例如发光二极管和用于在接通和/或断开时使通过发光器件的电流达峰化的装置。 峰化装置包括与发光装置并联布置并且是无源网络的峰化网络。

    Digital phase comparator
    6.
    发明授权
    Digital phase comparator 失效
    数字相位比较器

    公开(公告)号:US5990673A

    公开(公告)日:1999-11-23

    申请号:US765595

    申请日:1997-06-03

    Inventor: Gunnar Forsberg

    CPC classification number: G01R25/00 H03D13/00 H03L7/085 H03L7/18

    Abstract: The phase difference of two periodic input signals having essentially the same frequency are measured in, for example, a communication system, in an accurate way with a high resolution and utilizing digital components. A high resolution digital phase detector which can be included in a phase locked loop comprises an oscillator providing a clock signal having a high frequency that is not an integer multiple of the frequency of the input signals. The clock signal is provided to a clock signal input of a counter, and the periodic signals are fed to the start and stop terminals of the counter. Output terminals of the counter are directly connected to inputs of a digital low-pass filter in which an average value calculation is carried out of the integer values of the output of the counter. Because of the small frequency deviation from the integer multiple value, a slow sliding of the oscillator phase compared to the phase of the input signals is achieved, such that all possible integer values on the output of the counter are run through. A very accurate calculation of the phase position is achieved by the average value calculation of these integer values in the low-pass filter. In a complete phase-locked loop, a voltage controlled oscillator provides one of the input signals to the counter through a divider circuit.

    Abstract translation: PCT No.PCT / SE95 / 00813 Sec。 371日期:1997年6月3日 102(e)日期1997年6月3日PCT归档1995年6月30日PCT公布。 公开号WO96 / 01007 日期1996年1月11日具有基本上相同频率的两个周期性输入信号的相位差在例如通信系统中以高分辨率和利用数字分量的精确方式被测量。 可以包括在锁相环中的高分辨率数字相位检测器包括提供具有不是输入信号频率的整数倍的高频的时钟信号的振荡器。 时钟信号被提供给计数器的时钟信号输入,并且周期信号被馈送到计数器的起始和停止端子。 计数器的输出端子直接连接到数字低通滤波器的输入端,其中计数器的输出的整数值进行平均值计算。 由于与整数倍值的偏差小,所以实现了振荡器相位与输入信号的相位相比较慢的滑动,使得计数器的输出上的所有可能的整数值都通过。 通过低通滤波器中这些整数值的平均值计算,可以非常准确地计算相位位置。 在一个完整的锁相环中,压控振荡器通过分频电路向计数器提供一个输入信号。

    DATA TRANSMISSION INVOLVING MULTIPLEXING AND DEMULTIPLEXING OF EMBEDDED CLOCK SIGNALS
    7.
    发明申请
    DATA TRANSMISSION INVOLVING MULTIPLEXING AND DEMULTIPLEXING OF EMBEDDED CLOCK SIGNALS 有权
    涉及嵌入式时钟信号的多路复用和解复用的数据传输

    公开(公告)号:US20130039369A1

    公开(公告)日:2013-02-14

    申请号:US13643706

    申请日:2010-04-27

    Inventor: Gunnar Forsberg

    CPC classification number: H04J3/1664 H04L1/0025 H04L5/14 H04L5/26 H04L7/0083

    Abstract: In a data transmission system, a first node (100) receives at least two sets of input data signals (d-in1, d-in2) including at least two signals being based on different synchronization sources. The first node (100) extracts a respective clock signal (CLKex1, CLKex2) representing the embedded clock signals from said sources, samples and then formats these signals (CLKsp1, CLKsp2) for transmission according to a TDM structure. The TDM formatted signals are transmitted as at least one bit stream (bs1, bs2) over a transmission medium (L1, L2) to at least one second node (201, 202), where the bit stream (bs1, bs2) is demultiplexed into at least two sets of output data signals (d-out1, d-out2, d-out3, d-out4) respective demultiplexed clock signals (CLKdm1, CLKdm2) representing the sampled clock signals. A jitter attenuating means reduces, in each demultiplexed clock signal (CLKdm1, CLKdm2), an amount of frequency jitter to below a predefined level, and thus produces a respective clock signal having a synchronization quality being superior to the synchronization quality of the demultiplexed clock signals (CLKdm1, CLKdm2). An interface module (221, 222, 223, 224) recombines each data signal (d-out1, d-out2, d-out3, d-out4) with its associated clock signal into a respective resulting clock-carrying data signal (d-res 1, d-res2, d-res3, d-res4).

    Abstract translation: 在数据传输系统中,第一节点(100)接收包括基于不同同步源的至少两个信号的至少两组输入数据信号(d-in1,d-in2)。 第一节点(100)提取表示来自所述源的嵌入式时钟信号的相应时钟信号(CLKex1,CLKex2)采样,然后根据TDM结构格式化用于传输的这些信号(CLKsp1,CLKsp2)。 TDM格式的信号作为至少一个比特流(bs1,bs2)通过传输介质(L1,L2)发送到至少一个第二节点(201,202),其中比特流(bs1,bs2)被解复用 至少两组输出数据信号(d-out1,d-out2,d-out3,d-out4)表示采样的时钟信号的各个解复用时钟信号(CLKdm1,CLKdm2)。 抖动衰减装置将每个解复用的时钟信号(CLKdm1,CLKdm2)中的频率抖动量降低到低于预定电平,从而产生具有优于解复用的时钟信号的同步质量的相应时钟信号 (CLKdm1,CLKdm2)。 接口模块(221,222,223,224)将每个数据信号(d-out1,d-out2,d-out3,d-out4)与其关联的时钟信号复合成相应的所生成的时钟传送数据信号(d- res 1,d-res2,d-res3,d-res4)。

    Device for controlling the current through a PN junction
    8.
    发明授权
    Device for controlling the current through a PN junction 有权
    用于控制通过PN结的电流的装置

    公开(公告)号:US07911157B2

    公开(公告)日:2011-03-22

    申请号:US12596011

    申请日:2008-03-27

    CPC classification number: H05B33/0812 Y02B20/343 Y02B20/345

    Abstract: Device for controlling the current through a PN junction includes a voltage source connected in series to, in order, firstly a controllable current generator having an input connected to the voltage source, an output and a control input, thereafter a measurement resistor connected to the output, and finally a controlled output to which the PN junction is connected. The device further includes a control signal input, a differential amplifier and an integrating device, which includes a balanced integrator. The current through the output of the controllable current generator is proportional to the voltage difference between its input and its control input, and the reference voltage of the integrating device is constituted of the voltage of the voltage source.

    Abstract translation: 用于控制通过PN结的电流的装置包括串联连接的电压源,依次首先是具有连接到电压源的输入的可控电流发生器,输出和控制输入,之后连接到输出的测量电阻器 ,最后是连接PN结的受控输出。 该装置还包括控制信号输入,差分放大器和积分装置,其包括平衡积分器。 通过可控电流发生器的输出的电流与其输入与其控制输入之间的电压差成比例,并且积分装置的参考电压由电压源的电压构成。

    DEVICE FOR CONTROLLING THE CURRENT THROUGH A PN JUNCTION
    9.
    发明申请
    DEVICE FOR CONTROLLING THE CURRENT THROUGH A PN JUNCTION 有权
    通过PN接头控制电流的装置

    公开(公告)号:US20100244925A1

    公开(公告)日:2010-09-30

    申请号:US12596011

    申请日:2008-03-27

    CPC classification number: H05B33/0812 Y02B20/343 Y02B20/345

    Abstract: Device for controlling the current through a PN junction includes a voltage source connected in series to, in order, firstly a controllable current generator having an input connected to the voltage source, an output and a control input, thereafter a measurement resistor connected to the output, and finally a controlled output to which the PN junction is connected. The device further includes a control signal input, a differential amplifier and an integrating device, which includes a balanced integrator. The current through the output of the controllable current generator is proportional to the voltage difference between its input and its control input, and the reference voltage of the integrating device is constituted of the voltage of the voltage source.

    Abstract translation: 用于控制通过PN结的电流的装置包括串联连接的电压源,依次首先是具有连接到电压源的输入的可控电流发生器,输出和控制输入,之后连接到输出的测量电阻器 ,最后是连接PN结的受控输出。 该装置还包括控制信号输入,差分放大器和积分装置,其包括平衡积分器。 通过可控电流发生器的输出的电流与其输入与其控制输入之间的电压差成比例,并且积分装置的参考电压由电压源的电压构成。

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