公开(公告)号：US08853764B1

公开(公告)日：2014-10-07

申请号：US13832682

申请日：2013-03-15

申请人： Guowei Zhang ,  Deyan Chen

发明人： Guowei Zhang ,  Deyan Chen

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7817 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A method for forming a low Rdson LDNMOS and a high sheet resistance poly resistor and the resulting device are provided. Embodiments include forming first, second, and third STI regions in a substrate; forming a P-well in the substrate around the first STI region with a first mask; forming an N-drift region in the substrate between the P-well and the third STI region with the first mask; forming a dielectric layer over the substrate; forming a poly-silicon layer over the dielectric layer; performing an N-drain implant between the second and third STI regions with a second mask; performing a resistance adjustment implant in, but not through, the poly-silicon layer with the second mask; and patterning the poly-silicon and dielectric layers subsequent to performing the resistance adjustment implant to form a gate stack and a poly resistor, the poly resistor being formed over the third STI region and laterally separated from the gate stack.

摘要翻译： 提供了用于形成低Rdson LDNMOS和高电阻聚电阻器的方法以及所得到的器件。 实施例包括在衬底中形成第一，第二和第三STI区域; 用第一掩模在第一STI区周围的衬底中形成P阱; 在具有第一掩模的P阱和第三STI区之间的衬底中形成N漂移区; 在所述衬底上形成介电层; 在所述电介质层上形成多晶硅层; 在第二和第三STI区域之间用第二掩模执行N-漏极注入; 在所述第二掩模中对所述多晶硅层进行电阻调整注入，但不通过所述多晶硅层; 以及在执行所述电阻调节注入之后构图所述多晶硅和电介质层以形成栅极堆叠和多晶硅电阻器，所述多晶硅电阻器形成在所述第三STI区域上并且与所述栅极叠层横向分离。

公开(公告)号：US08809150B2

公开(公告)日：2014-08-19

申请号：US13587059

申请日：2012-08-16

申请人： Guowei Zhang ,  Purakh Raj Verma ,  Zhiqing Li

发明人： Guowei Zhang ,  Purakh Raj Verma ,  Zhiqing Li

IPC分类号： H01L21/336

CPC分类号： H01L29/7834 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7835

摘要： LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches.

摘要翻译： 在具有减小厚度的多晶硅层和源极/漏极结的器件中，LDD区域具有高的注入能量。 实施例包括在衬底表面上形成氧化物层，在氧化物层上形成多晶硅层，通过氧化物层和多晶硅层并在衬底表面之下形成第一和第二沟槽，在衬底表面之下限定栅极区域，注入掺杂剂 在通过第一和第二沟槽的LDD区域中，在栅极区域的相对侧表面上形成间隔物并且延伸到第一和第二沟槽中，并且在第一和第二沟槽中的每一个下方的源极/漏极区域中注入掺杂剂。

公开(公告)号：US20130093012A1

公开(公告)日：2013-04-18

申请号：US13276301

申请日：2011-10-18

申请人： Guowei ZHANG ,  Purakh Raj VERMA ,  Baofu ZHU

发明人： Guowei ZHANG ,  Purakh Raj VERMA ,  Baofu ZHU

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7823 ,  H01L29/7835

摘要： A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.

摘要翻译： 公开了一种形成装置的方法。 该方法包括提供具有器件区域的衬底。 器件区域包括限定在其上的源极区域，栅极区域和漏极区域。 在衬底上用栅极层制备衬底。 栅极层被图案化以在栅极区域中形成栅极，并且围绕漏极区域形成场结构。 在源极区和漏极区分别形成源极和漏极。 漏极在栅极的第二侧与栅极分离，并且源极与栅极的第一侧相邻。 形成与场结构的互连。 互连耦合到在栅极和漏极的第二侧之间跨越衬底分布电场的电势。

公开(公告)号：US08334567B2

公开(公告)日：2012-12-18

申请号：US12916653

申请日：2010-11-01

申请人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

发明人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

IPC分类号： H01L29/76

CPC分类号： H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

摘要： First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.

摘要翻译： 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力。

公开(公告)号：US20110042743A1

公开(公告)日：2011-02-24

申请号：US12916653

申请日：2010-11-01

申请人： Sanford CHU ,  Yisuo LI ,  Guowei ZHANG ,  Purakh Raj VERMA

发明人： Sanford CHU ,  Yisuo LI ,  Guowei ZHANG ,  Purakh Raj VERMA

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

摘要： First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region

摘要翻译： 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力

公开(公告)号：US07824968B2

公开(公告)日：2010-11-02

申请号：US11488117

申请日：2006-07-17

申请人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

发明人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

IPC分类号： H01L21/332 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

摘要： First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.

摘要翻译： 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力。

公开(公告)号：US20080014690A1

公开(公告)日：2008-01-17

申请号：US11488117

申请日：2006-07-17

申请人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

发明人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

IPC分类号： H01L21/8234

CPC分类号： H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

摘要： First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region

摘要翻译： 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力

公开(公告)号：US20060134882A1

公开(公告)日：2006-06-22

申请号：US11021030

申请日：2004-12-22

申请人： Guowei Zhang

发明人： Guowei Zhang

IPC分类号： H01L21/76

CPC分类号： H01L21/76237 ,  H01L21/26506 ,  H01L21/76235

摘要： A method of forming a shallow trench isolation (STI) structure wherein the depth of the STI structure has been extended via formation of an underlying silicon oxide region, has been developed. After definition of a shallow trench isolation shape in a top portion of a semiconductor substrate a self-aligned ion implantation procedure is employed to place oxygen ions in portions of the semiconductor substrate exposed at the bottom portion of the shallow trench shape. Growth of a liner layer on the exposed surfaces of the shallow trench shape, or growth of a liner layer followed by anneal procedure, results in activation of the implanted oxygen ions creating the desired silicon oxide region in a portion of the semiconductor substrate underlying the bottom of the shallow trench shape. Insulator filling of the shallow trench shape now results in a deeper STI structure comprised of the insulator filled shallow trench shape and the underlying silicon oxide region.

摘要翻译： 已经开发出形成浅沟槽隔离（STI）结构的方法，其中通过形成下面的氧化硅区域已经延伸了STI结构的深度。 在半导体衬底的顶部部分中定义浅沟槽隔离形状之后，采用自对准离子注入程序将氧离子放置在浅沟槽形状底部暴露的部分半导体衬底中。 在浅沟槽形状的暴露表面上的衬垫层的生长或者衬底层的生长随后退火过程导致注入的氧离子的活化，在半导体衬底底部的一部分中产生所需的氧化硅区域 的浅沟槽形状。 浅沟槽形状的绝缘体填充现在形成了由绝缘体填充的浅沟槽形状和下面的氧化硅区域组成的更深的STI结构。

公开(公告)号：USD966499S1

公开(公告)日：2022-10-11

申请号：US29820440

申请日：2021-12-22

申请人： Guowei Zhang

设计人： Guowei Zhang

公开(公告)号：US08790966B2

公开(公告)日：2014-07-29

申请号：US13276301

申请日：2011-10-18

申请人： Guowei Zhang ,  Purakh Raj Verma ,  Baofu Zhu

发明人： Guowei Zhang ,  Purakh Raj Verma ,  Baofu Zhu

IPC分类号： H01L21/332

CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7823 ,  H01L29/7835

摘要： A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.

摘要翻译： 公开了一种形成装置的方法。 该方法包括提供具有器件区域的衬底。 器件区域包括限定在其上的源极区域，栅极区域和漏极区域。 在衬底上用栅极层制备衬底。 栅极层被图案化以在栅极区域中形成栅极，并且围绕漏极区域形成场结构。 在源极区和漏极区分别形成源极和漏极。 漏极在栅极的第二侧与栅极分离，并且源极与栅极的第一侧相邻。 形成与场结构的互连。 互连耦合到在栅极和漏极的第二侧之间跨越衬底分布电场的电势。