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    Balanced P-LRU tree for a “multiple of 3” number of ways cache
    1.
    发明授权
    Balanced P-LRU tree for a “multiple of 3” number of ways cache 有权
    平衡的P-LRU树为“多个3”的缓存方式

    公开(公告)号：US09348766B2

    公开(公告)日：2016-05-24

    申请号：US13994690

    申请日：2011-12-21

    申请人： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    发明人： Adi Basel ,  Gur Hildesheim ,  Shlomo Raikin ,  Robert Chappell ,  Ho-Seop Kim ,  Rohit Bhatia

    IPC分类号： G06F13/00 ,  G06F12/12 ,  G06F3/06 ,  G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/122 ,  G06F3/0604 ,  G06F12/00 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/124 ,  G06F12/125

    摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.

    摘要翻译： 根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。 在这样的实施例中，多个方式包括量是三的倍数而不是二的幂，并且其中多个方式被组织成多对。 在这种实施例中，装置还包括用于多个对中的每一对的单个比特，其中每个单个比特将用作表示相关联的一对路由的中间级别决策节点，以及具有正好两个单独比特的根级别决策节点 指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。 在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。 还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

    Concurrent page table walker control for TLB miss handling
    2.
    发明授权
    Concurrent page table walker control for TLB miss handling 有权
    用于TLB未命中处理的并发页表步行控制

    公开(公告)号：US09069690B2

    公开(公告)日：2015-06-30

    申请号：US13613777

    申请日：2012-09-13

    申请人： Gur Hildesheim ,  Chang Kian Tan ,  Robert S. Chappell ,  Rohit Bhatia

    发明人： Gur Hildesheim ,  Chang Kian Tan ,  Robert S. Chappell ,  Rohit Bhatia

    IPC分类号： G06F12/10

    CPC分类号： G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/651 ,  G06F2212/655 ,  G06F2212/681 ,  G06F2212/684

    摘要： In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并且从寻呼结构获得物理地址的对应部分，与第一步行者并行操作的第二步行者，以及 用于防止第一步行器响应于匹配由第二步行者访问的并行寻呼结构的对应线性地址部分的第一线性地址部分而将所获得的物理地址部分存储在寻呼高速缓存器中的逻辑。 描述和要求保护其他实施例。

    ACCESS TYPE PROTECTION OF MEMORY RESERVED FOR USE BY PROCESSOR LOGIC
    3.
    发明申请
    ACCESS TYPE PROTECTION OF MEMORY RESERVED FOR USE BY PROCESSOR LOGIC 有权
    存储器访问类型保护由处理器逻辑使用

    公开(公告)号：US20140189261A1

    公开(公告)日：2014-07-03

    申请号：US13729439

    申请日：2012-12-28

    申请人： GUR HILDESHEIM ,  SHLOMO RAIKIN ,  ITTAI ANATI ,  GIDEON GERZON ,  HISHAM SHAFI ,  ALEX BERENZON ,  GEOFFREY S. STRONGIN ,  IRIS SORANI

    发明人： GUR HILDESHEIM ,  SHLOMO RAIKIN ,  ITTAI ANATI ,  GIDEON GERZON ,  HISHAM SHAFI ,  ALEX BERENZON ,  GEOFFREY S. STRONGIN ,  IRIS SORANI

    IPC分类号： G06F12/14

    CPC分类号： G06F12/1027 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1052

    摘要： A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access.

    摘要翻译： 一方面的处理器包括操作模式检查逻辑，用于基于用于指示尝试访问是否由片上处理器逻辑的操作模式来确定是否允许尝试访问操作模式和访问类型受保护存储器。 访问类型检查逻辑是基于尝试访问操作模式和访问类型受保护的存储器的访问类型来确定是否允许尝试访问操作模式和访问类型受保护的存储器。 保护逻辑与操作模式检查逻辑耦合，并与访问类型检查逻辑耦合。 如果操作模式检查逻辑和访问类型检查逻辑中的至少一个确定不允许尝试访问，则保护逻辑是拒绝尝试访问操作模式和访问类型保护的存储器。

    Concurrent Control For A Page Miss Handler
    4.
    发明申请
    Concurrent Control For A Page Miss Handler 有权
    并发控制页面小姐处理程序

    公开(公告)号：US20140075123A1

    公开(公告)日：2014-03-13

    申请号：US13613777

    申请日：2012-09-13

    申请人： Gur HILDESHEIM ,  Chang Kian TAN ,  Robert S. CHAPPELL ,  Rohit BHATIA

    发明人： Gur HILDESHEIM ,  Chang Kian TAN ,  Robert S. CHAPPELL ,  Rohit BHATIA

    IPC分类号： G06F12/10

    CPC分类号： G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/651 ,  G06F2212/655 ,  G06F2212/681 ,  G06F2212/684

    摘要： In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并从寻呼结构获得物理地址的对应部分，与第一步行者同时操作的第二步行者， 逻辑，用于防止第一步行者将所获得的物理地址部分存储在响应于第一线性地址部分匹配第二步行者的并发寻呼结构访问的相应线性地址部分的寻呼高速缓存中。 描述和要求保护其他实施例。

    APPARATUS AND METHOD FOR A MULTIPLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER (TLB)
    9.
    发明申请
    APPARATUS AND METHOD FOR A MULTIPLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER (TLB) 审中-公开
    多页翻页预处理缓存器（TLB）的设备和方法

    公开(公告)号：US20140189192A1

    公开(公告)日：2014-07-03

    申请号：US13730411

    申请日：2012-12-28

    申请人： Shlomo Raikin ,  Oren Hamama ,  Robert S. Chappell ,  Camron B. Rust ,  Han S. Luu ,  Leslie A. Ong ,  Gur Hildesheim

    发明人： Shlomo Raikin ,  Oren Hamama ,  Robert S. Chappell ,  Camron B. Rust ,  Han S. Luu ,  Leslie A. Ong ,  Gur Hildesheim

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F2212/652 ,  Y02D10/13

    摘要： An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size.

    摘要翻译： 一种用于实现多页尺寸翻译后备缓冲器（TLB）的装置和方法。 例如，根据一个实施例的方法包括：从线性地址读取第一组位和第二组位; 确定线性地址是否与大页面尺寸或小页面尺寸相关联; 如果所述线性地址与第一页面尺寸相关联，则使用所述第一组位标识第一高速缓存集合，并且如果所述线性地址与第二页面尺寸相关联则使用所述第二组位标识第二高速缓存集合; 以及如果所述线性地址与第一页面尺寸相关联并且如果所述线性地址与第二页面尺寸相关联则识别第二高速缓存路线，则识别第一高速缓存路线。