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公开(公告)号：US06810372B1
公开(公告)日：2004-10-26
申请号：US09456953
申请日：1999-12-07
IPC分类号： G06F1750
CPC分类号： G01R31/318371
摘要： A method of and system for generating tests and using the tests to identify VLSI simulation and circuit operation faults and errors and validate performance uses a genetic algorithm. Each generation of tests is further processed to eliminate redundant tests and make room for the insertion of new genetic material into the population in the form of random test vectors. The resulting family of tests generated using a simulation of the VLSI can then be ported to the circuit once prototyped in silicon and adapted to the new environment using, once again, the genetic algorithm to suitably evolve the test population.
摘要翻译： 用于生成测试和使用测试来识别VLSI仿真和电路运行故障和错误并验证性能的方法和系统使用遗传算法。 进一步处理每一代测试以消除冗余测试，并为随机测试载体形式的新遗传物质插入群体腾出空间。 使用VLSI的仿真产生的所得到的测试系列随后可以在硅中原型化之后移植到电路中，并且适用于新的环境，再次使用遗传算法来适当地演化测试群体。
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公开(公告)号：US20140223045A1
公开(公告)日：2014-08-07
申请号：US13997906
申请日：2012-01-18
IPC分类号： G06F13/40 , G06F13/374
CPC分类号： G06F13/4018 , G06F13/374 , G06F13/4072 , G06F2213/0026 , H03M9/00
摘要： Embodiments of the invention describe an apparatus, system and method for executing self-correction logic for serial-to-parallel data converters. Embodiments of the invention receive one of a plurality of serial data streams from a peripheral device, each of the serial data streams having one or more bits. In response to detecting that a shift register chain includes a register select value, embodiments of the invention may store the received serial data stream in one of a plurality of data registers, wherein the one data register is selected based, at least in part, on a position of the register select value in the shift register chain. In response to detecting the shift register chain does contain the register select value, embodiments of the invention may insert the register select value at a register of the shift register chain.
摘要翻译： 本发明的实施例描述了一种用于执行串行到并行数据转换器的自校正逻辑的装置，系统和方法。 本发明的实施例从外围设备接收多个串行数据流中的一个，每个串行数据流具有一个或多个位。 响应于检测到移位寄存器链包括寄存器选择值，本发明的实施例可以将所接收的串行数据流存储在多个数据寄存器之一中，其中，所述一个数据寄存器至少部分地基于 移位寄存器链中寄存器选择值的位置。 响应于检测到移位寄存器链确实包含寄存器选择值，本发明的实施例可以将寄存器选择值插入移位寄存器链的寄存器。
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3.发明申请INCREASING INPUT OUTPUT HUBS IN CONSTRAINED LINK BASED MULTI-PROCESSOR SYSTEMS 有权在基于链路的多处理器系统中增加输入输出HUBS公开(公告)号：US20120226848A1
公开(公告)日：2012-09-06
申请号：US13039119
申请日：2011-03-02
IPC分类号： G06F13/20
CPC分类号： G06F13/387
摘要： Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are coupled a link interconnect and a plurality of processors, coupled to the first and second IOHs include pre-allocated resources for a single IOH. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了在基于约束链路的多处理器系统中增加输入输出中枢的方法和装置。 在一个实施例中，耦合到链路互连的第一输入输出集线器（IOH）和第二IOH耦合到耦合到第一和第二IOH的多个处理器包括用于单个IOH的预先分配的资源。 还公开并要求保护其他实施例。
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公开(公告)号：US07770051B2
公开(公告)日：2010-08-03
申请号：US12235532
申请日：2008-09-22
CPC分类号： H04L49/9078 , H04L49/90
摘要： Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.
摘要翻译： 本发明的各种实施例提供一种频率移位器来改变随时间传输的数据的频率，诸如增加和减少随时间传输的测试数据的频率，以验证数字通信设备接收具有特定参数内的各种频率的数据的能力 范围。 频移器包括频率修正器，用于将输入时钟频率移位或改变为各种输出时钟频率，例如根据测试协议。 移相器还包括一个弹性数据缓冲器，用于以输入时钟频率接收测试数据，并输出由频率调节器提供的多个输出时钟频率的测试数据。
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公开(公告)号：US09164943B2
公开(公告)日：2015-10-20
申请号：US13997906
申请日：2012-01-18
IPC分类号： G06F3/00 , G06F13/12 , G06F11/00 , H03M13/00 , G06F11/10 , H04L7/00 , G06F13/40 , H03M9/00 , G06F13/374
CPC分类号： G06F13/4018 , G06F13/374 , G06F13/4072 , G06F2213/0026 , H03M9/00
摘要： Embodiments of the invention describe an apparatus, system and method for executing self-correction logic for serial-to-parallel data converters. Embodiments of the invention receive one of a plurality of serial data streams from a peripheral device, each of the serial data streams having one or more bits. In response to detecting that a shift register chain includes a register select value, embodiments of the invention may store the received serial data stream in one of a plurality of data registers, wherein the one data register is selected based, at least in part, on a position of the register select value in the shift register chain. In response to detecting the shift register chain does contain the register select value, embodiments of the invention may insert the register select value at a register of the shift register chain.
摘要翻译： 本发明的实施例描述了一种用于执行串行到并行数据转换器的自校正逻辑的装置，系统和方法。 本发明的实施例从外围设备接收多个串行数据流中的一个，每个串行数据流具有一个或多个位。 响应于检测到移位寄存器链包括寄存器选择值，本发明的实施例可以将所接收的串行数据流存储在多个数据寄存器之一中，其中，所述一个数据寄存器至少部分地基于 移位寄存器链中寄存器选择值的位置。 响应于检测到移位寄存器链确实包含寄存器选择值，本发明的实施例可以将寄存器选择值插入移位寄存器链的寄存器。
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6.发明授权Increasing Input Output Hubs in constrained link based multi-processor systems 有权在基于约束链路的多处理器系统中增加输入输出集线器公开(公告)号：US08782318B2
公开(公告)日：2014-07-15
申请号：US13039119
申请日：2011-03-02
CPC分类号： G06F13/387
摘要： Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are coupled a link interconnect and a plurality of processors, coupled to the first and second IOHs include pre-allocated resources for a single IOH. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了在基于约束链路的多处理器系统中增加输入输出中枢的方法和装置。 在一个实施例中，耦合到链路互连的第一输入输出集线器（IOH）和第二IOH耦合到耦合到第一和第二IOH的多个处理器包括用于单个IOH的预先分配的资源。 还公开并要求保护其他实施例。
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公开(公告)号：US20100199120A1
公开(公告)日：2010-08-05
申请号：US12756998
申请日：2010-04-08
IPC分类号： G06F1/04
CPC分类号： H04L49/9078 , H04L49/90
摘要： Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.
摘要翻译： 本发明的各种实施例提供一种频率移位器来改变随时间传输的数据的频率，诸如增加和减少随时间传输的测试数据的频率，以验证数字通信设备接收具有特定参数内的各种频率的数据的能力 范围。 频移器包括频率修正器，用于将输入时钟频率移位或改变为各种输出时钟频率，例如根据测试协议。 移相器还包括一个弹性数据缓冲器，用于以输入时钟频率接收测试数据，并输出由频率调节器提供的多个输出时钟频率的测试数据。
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公开(公告)号：US07464287B2
公开(公告)日：2008-12-09
申请号：US10815903
申请日：2004-03-31
CPC分类号： H04L49/9078 , H04L49/90
摘要： Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.
摘要翻译： 本发明的各种实施例提供一种频率移位器来改变随时间传输的数据的频率，诸如增加和减少随时间传输的测试数据的频率，以验证数字通信设备接收具有特定参数内的各种频率的数据的能力 范围。 频移器包括频率修正器，用于将输入时钟频率移位或改变为各种输出时钟频率，例如根据测试协议。 移相器还包括一个弹性数据缓冲器，用于以输入时钟频率接收测试数据，并输出由频率调节器提供的多个输出时钟频率的测试数据。
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公开(公告)号：US08209563B2
公开(公告)日：2012-06-26
申请号：US12756998
申请日：2010-04-08
CPC分类号： H04L49/9078 , H04L49/90
摘要： Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.
摘要翻译： 本发明的各种实施例提供一种频率移位器来改变随时间传输的数据的频率，诸如增加和减少随时间传输的测试数据的频率，以验证数字通信设备接收具有特定参数内的各种频率的数据的能力 范围。 频移器包括频率修正器，用于将输入时钟频率移位或改变为各种输出时钟频率，例如根据测试协议。 移相器还包括一个弹性数据缓冲器，用于以输入时钟频率接收测试数据，并输出由频率调节器提供的多个输出时钟频率的测试数据。
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公开(公告)号：US20090016381A1
公开(公告)日：2009-01-15
申请号：US12235532
申请日：2008-09-22
IPC分类号： H04J1/00
CPC分类号： H04L49/9078 , H04L49/90
摘要： Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.
摘要翻译： 本发明的各种实施例提供一种频率移位器来改变随时间传输的数据的频率，诸如增加和减少随时间传输的测试数据的频率，以验证数字通信设备接收具有特定参数内的各种频率的数据的能力 范围。 频移器包括频率修正器，用于将输入时钟频率移位或改变为各种输出时钟频率，例如根据测试协议。 移相器还包括一个弹性数据缓冲器，用于以输入时钟频率接收测试数据，并输出由频率调节器提供的多个输出时钟频率的测试数据。
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