公开(公告)号：US09727409B2

公开(公告)日：2017-08-08

申请号：US14739534

申请日：2015-06-15

申请人： Sang-Hoon Shin ,  Hae-Suk Lee ,  Han-Vit Jung ,  Kyo-Min Sohn

发明人： Sang-Hoon Shin ,  Hae-Suk Lee ,  Han-Vit Jung ,  Kyo-Min Sohn

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20

CPC分类号： G06F11/0793 ,  G06F11/0703 ,  G06F11/0796 ,  G06F11/142 ,  G06F11/1423 ,  G06F11/1616 ,  G06F11/18 ,  G06F11/2002 ,  G06F11/2017

摘要： A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

公开(公告)号：US20160048425A1

公开(公告)日：2016-02-18

申请号：US14722823

申请日：2015-05-27

申请人： Hyun-joong Kim ,  Soo-hyeong Kim ,  Sang-hoon Shin ,  Ju-yun Jung ,  Ho-young Song ,  Kyo-min Sohn ,  Hae-suk Lee ,  Bu-il Jung ,  Han-vit Jeong

发明人： Hyun-joong Kim ,  Soo-hyeong Kim ,  Sang-hoon Shin ,  Ju-yun Jung ,  Ho-young Song ,  Kyo-min Sohn ,  Hae-suk Lee ,  Bu-il Jung ,  Han-vit Jeong

IPC分类号： G06F11/10 ,  G11C29/52

CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C2029/0411

摘要： A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.

摘要翻译： 一种存储器件，包括：纠错码（ECC）单元阵列; ECC引擎，被配置为接收要写入存储单元阵列的写入数据，并为写入数据生成内部奇偶校验位; 以及ECC选择单元，被配置为接收内部奇偶校验位和外部奇偶校验位，并且响应于控制信号的第一电平将内部奇偶校验位存储在ECC单元阵列中，并且响应于第二级别的控制 信号存储ECC单元阵列中的外部奇偶校验位。