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公开(公告)号：US20140003550A1
公开(公告)日：2014-01-02
申请号：US13536567
申请日：2012-06-28
IPC分类号： H04L27/00
CPC分类号： H04L27/00 , G11C7/04 , G11C7/22 , H03K5/133 , H03K5/1565 , H04L25/03343
摘要： Disclosed embodiments may include a circuit having a clock-to-output (TCO) compensation circuit coupled to a RAM pull-up transmitter and a RAM pull-down transmitter. The TCO compensation circuit may be configured to compare a first output with a second output and to generate a delay code, based on the comparison, for at least one other RAM transmitter on the die to adjust a duty cycle of a third output associated with the at least one other RAM transmitter. Other embodiments may be disclosed.
摘要翻译： 公开的实施例可以包括具有耦合到RAM上拉发送器和RAM下拉发送器的时钟到输出（TCO）补偿电路的电路。 TCO补偿电路可以被配置为将第一输出与第二输出进行比较，并且基于比较来生成针对芯片上的至少一个其他RAM发送器的延迟码，以调整与第二输出相关联的第三输出的占空比 至少一个其他RAM发送器。 可以公开其他实施例。
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公开(公告)号：US20090085623A1
公开(公告)日：2009-04-02
申请号：US11864921
申请日：2007-09-29
IPC分类号： H03L7/08
CPC分类号： H03L7/07 , H03L7/0805 , H03L7/0812
摘要： Provided herein are approaches for controlling remote slave DLL circuits with a master DLL circuit by conveying a relevant bias signal as a current signal instead of as a voltage signal.
摘要翻译： 本文提供了通过传送相关偏置信号作为电流信号而不是作为电压信号来控制具有主DLL电路的远程从属DLL电路的方法。
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公开(公告)号：US06791428B2
公开(公告)日：2004-09-14
申请号：US10331805
申请日：2002-12-30
IPC分类号： H03B532
CPC分类号： H03B5/36
摘要： A circuit for producing a reliable duty cycle for a low power oscillator. The circuit produces a square wave signal based on the differences between the oscillating output signal driven by a piezoelectric crystal and a phase shifted output signal. This circuit provides a quick start for a clock signal, generates a reliable fifty percent duty cycle and is better protected from common mode noise. This circuit can also be configured to be programmable to provide for an adjustable duty cycle.
摘要翻译： 用于为低功耗振荡器产生可靠占空比的电路。 该电路基于由压电晶体驱动的振荡输出信号和相移输出信号之间的差异产生方波信号。 该电路为时钟信号提供快速启动，产生可靠的百分之五十的占空比，并且更好地防止共模噪声。 该电路也可以被配置为可编程以提供可调整的占空比。
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公开(公告)号：US20120019285A1
公开(公告)日：2012-01-26
申请号：US12840691
申请日：2010-07-21
IPC分类号： H03K3/01
CPC分类号： H03K17/22 , H03K19/0008
摘要： Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.
摘要翻译： 这里描述了以最小延迟来唤醒模拟偏置信号的方法和装置。 该装置包括第一逻辑单元，用于响应于断电事件经由第一预定信号调节门控偏置信号的信号电平; 比较器，用于将门控偏置信号与非门控偏置信号进行比较，并且可操作以产生指示比较结果的输出信号; 以及耦合到所述比较器的自定时逻辑单元，用于响应于所述断电事件和所述输出信号的结束而产生唤醒信号。
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公开(公告)号：US07795935B2
公开(公告)日：2010-09-14
申请号：US11864921
申请日：2007-09-29
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0805 , H03L7/0812
摘要： Provided herein are approaches for controlling remote slave DLL circuits with a master DLL circuit by conveying a relevant bias signal as a current signal instead of as a voltage signal.
摘要翻译： 本文提供了通过传送相关偏置信号作为电流信号而不是作为电压信号来控制具有主DLL电路的远程从属DLL电路的方法。
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公开(公告)号：US20060245473A1
公开(公告)日：2006-11-02
申请号：US11118227
申请日：2005-04-28
申请人： Roger Cheng , Navneet Dour , Scott Miller , David Freker , Harishankar Sridharan , Mahmood Alam
发明人： Roger Cheng , Navneet Dour , Scott Miller , David Freker , Harishankar Sridharan , Mahmood Alam
IPC分类号： H04B1/00
CPC分类号： G06F13/423 , Y02D10/14 , Y02D10/151
摘要： An embodiment of the present invention is a technique to integrate data for a source synchronous protocol. A delay generator generates at least an integrating strobe from a data strobe synchronizing a data having a data window using the source synchronous protocol. A pulse generator generates a pulse from the at least integrating strobe. An integrating receiver integrates the data over an integration window defined by the pulse. The integration window is within the data window.
摘要翻译： 本发明的一个实施例是用于集成源同步协议的数据的技术。 延迟发生器使用源同步协议从数据选通器产生至少一个使具有数据窗口的数据同步的积分选通脉冲。 脉冲发生器从至少积分选通脉冲产生脉冲。 积分接收器通过由脉冲定义的积分窗口来集成数据。 集成窗口在数据窗口内。
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公开(公告)号：US08350610B2
公开(公告)日：2013-01-08
申请号：US12840691
申请日：2010-07-21
IPC分类号： H03K3/02
CPC分类号： H03K17/22 , H03K19/0008
摘要： Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.
摘要翻译： 这里描述了以最小延迟来唤醒模拟偏置信号的方法和装置。 该装置包括第一逻辑单元，用于响应于断电事件经由第一预定信号调节门控偏置信号的信号电平; 比较器，用于将门控偏置信号与非门控偏置信号进行比较，并且可操作以产生指示比较结果的输出信号; 以及耦合到所述比较器的自定时逻辑单元，用于响应于所述断电事件和所述输出信号的结束而产生唤醒信号。
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公开(公告)号：US09049057B2
公开(公告)日：2015-06-02
申请号：US13536567
申请日：2012-06-28
CPC分类号： H04L27/00 , G11C7/04 , G11C7/22 , H03K5/133 , H03K5/1565 , H04L25/03343
摘要： Disclosed embodiments may include a circuit having a clock-to-output (TCO) compensation circuit coupled to a RAM pull-up transmitter and a RAM pull-down transmitter. The TCO compensation circuit may be configured to compare a first output with a second output and to generate a delay code, based on the comparison, for at least one other RAM transmitter on the die to adjust a duty cycle of a third output associated with the at least one other RAM transmitter. Other embodiments may be disclosed.
摘要翻译： 公开的实施例可以包括具有耦合到RAM上拉发送器和RAM下拉发送器的时钟到输出（TCO）补偿电路的电路。 TCO补偿电路可以被配置为将第一输出与第二输出进行比较，并且基于比较来生成针对芯片上的至少一个其他RAM发送器的延迟码，以调整与第二输出相关联的第三输出的占空比 至少一个其他RAM发送器。 可以公开其他实施例。
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公开(公告)号：US07746135B2
公开(公告)日：2010-06-29
申请号：US11864923
申请日：2007-09-29
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0802 , H03L7/0805 , H03L7/0812 , H03L7/10
摘要： Disclosed herein is a wake-up circuit for a bias input of a circuit such as a slave DLL circuit, to allow it to be placed in a reduced power mode and be “awoken” (brought up to a control bias level) in a sufficiently small enough amount of time. The wake-up circuit couples a bias input node to a voltage level that is higher then the control bias level in response to a wake-up event, and then it couples the control bias node to the bias input node in response to their voltage levels being sufficiently close to one another.
摘要翻译： 这里公开了一种用于诸如从属DLL电路的电路的偏置输入的唤醒电路，以允许其被放置在降低功率模式中并且被充分地“唤醒”（提高到控制偏置电平） 足够小的时间。 唤醒电路将偏置输入节点耦合到响应于唤醒事件的高于控制偏置电平的电压电平，然后响应于其电压电平将控制偏置节点耦合到偏置输入节点 充分接近彼此。
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公开(公告)号：US07602859B2
公开(公告)日：2009-10-13
申请号：US11118228
申请日：2005-04-28
IPC分类号： H04L27/00
CPC分类号： H04L25/20
摘要： An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of at least an integrating strobe used to define an integration window for the integrating receiver. An integrating receiver pulse generator generates an IR pulse from the at least integrating strobe. A calibration controller controls calibrating the adjusting code and the positioning of the at least integrating strobe.
摘要翻译： 本发明的实施例是校准积分接收器的技术。 延迟校准电路校准延迟元件链的调整代码，并且至少定位用于为积分接收器定义积分窗口的积分选通脉冲。 积分接收器脉冲发生器从至少积分选通器产生IR脉冲。 校准控制器控制校准调整代码和至少积分选通脉冲的定位。
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