公开(公告)号：US08086865B2

公开(公告)日：2011-12-27

申请号：US12116258

申请日：2008-05-07

申请人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Mohammad Peyravian

发明人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Mohammad Peyravian

IPC分类号： H04L9/12

CPC分类号： H04L9/3242

摘要： The present invention provides for authenticating a message, A security function is performed upon the message, The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.

摘要翻译： 本发明提供了对消息的认证，对该消息执行安全功能。该消息被发送到目标。 安全功能的输出被发送到目标。 至少有一个公认的常数被发送到目标。 接收到的消息被认证为至少共享密钥，接收的公知常数，安全功能，接收到的消息和安全功能的输出的功能。 如果目标接收到的安全功能的输出与至少作为接收到的消息的函数产生的输出相同，则所接收的已知常数，安全功能和共享密钥，消息和常数都不具有 被改变了

公开(公告)号：US07890561B2

公开(公告)日：2011-02-15

申请号：US11204402

申请日：2005-08-16

申请人： David William Boerstler ,  Eskinder Hailu ,  Harm Peter Hofstee ,  John Samuel Liberty

发明人： David William Boerstler ,  Eskinder Hailu ,  Harm Peter Hofstee ,  John Samuel Liberty

IPC分类号： G06F1/02 ,  G06F7/58

CPC分类号： G06F7/588 ,  H04L9/001 ,  H04L9/0869

摘要： A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.

摘要翻译： 提供随机数生成器，方法和计算机程序产品用于产生随机数种子。 振荡器阵列内的每个振荡器以不同的频率工作。 每个振荡器的工作频率不是谐波相关的，使得在任何两个振荡器的频率之间不存在整数倍。 在一个实施例中，振荡器阵列的输出连接到多输入锁存器。 多输入锁存器还接收作为时钟信号的采样信号。 时钟信号对振荡器阵列的输出采样，并且多输入锁存器与随机数确定逻辑（“RNDL”）一起为阵列内的每个振荡器产生数字输出（0或1）。 RNDL使用这些数字输出创建一个随机数字种子。

公开(公告)号：US20110019368A1

公开(公告)日：2011-01-27

申请号：US12507591

申请日：2009-07-22

申请人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

发明人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

IPC分类号： H05K1/18 ,  C23F1/00

CPC分类号： H01L25/0655 ,  H01L23/147 ,  H01L23/60 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/157 ,  Y02T10/82 ,  H01L2924/00

摘要： A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

摘要翻译： 一种用于电子封装的硅载体结构包括基底，设置在基底基板上的硅载体衬底，设置在硅载体衬底上的存储芯片，设置在硅载体衬底上的微处理器芯片，设置在硅衬底上的输入/输出芯片 硅载体衬底和设置在硅载体衬底上的时钟芯片。

公开(公告)号：US20090327728A1

公开(公告)日：2009-12-31

申请号：US12116258

申请日：2008-05-07

申请人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Mohammad Peyravian

发明人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Mohammad Peyravian

IPC分类号： H04L9/32

CPC分类号： H04L9/3242

摘要： The present invention provides for authenticating a message. A security function is performed upon the message. The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.

摘要翻译： 本发明提供用于认证消息。 对消息执行安全功能。 该消息被发送到目标。 安全功能的输出被发送到目标。 至少有一个公认的常数被发送到目标。 接收到的消息被认证为至少共享密钥，接收的公知常数，安全功能，接收到的消息和安全功能的输出的功能。 如果目标接收到的安全功能的输出与至少作为接收到的消息的函数产生的输出相同，则所接收的公知常数，安全功能和共享密钥，消息和常数都不具有 被改变了

公开(公告)号：US07620951B2

公开(公告)日：2009-11-17

申请号：US12049293

申请日：2008-03-15

申请人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Barry L Minor ,  Mark Richard Nutter

发明人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Barry L Minor ,  Mark Richard Nutter

IPC分类号： G06F9/46

CPC分类号： G06F9/322 ,  G06F8/41 ,  G06F9/3851

摘要： An approach to hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.

摘要翻译： 介绍了一种在多线程环境中隐藏内存延迟的方法。 分支间接和设置链接（BISL）和/或分支间接和设置链接，如果外部数据（BISLED）指令在对应于延长的指令的实例的编译期间被放置在线程代码中。 延长的指令是指示计算机系统中的延迟，例如DMA指令。 当第一个线程遇到BISL或BISLED指令时，第一个线程在第一个线程的延长指令执行时将控制传递给第二个线程。 反过来，计算机系统掩盖了第一个线程延长的指令的延迟。 可以通过创建更多线程并在线程之间进一步划分寄存器池来进一步隐藏高度内存限制的操作中的内存延迟，从而可以基于内存延迟来优化系统。

公开(公告)号：US07493357B2

公开(公告)日：2009-02-17

申请号：US10971851

申请日：2004-10-22

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Kevin Nowka ,  Steven Douglas Posluszny ,  Joel Abraham Silberman

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Kevin Nowka ,  Steven Douglas Posluszny ,  Joel Abraham Silberman

IPC分类号： G06F7/44 ,  G06F7/38

CPC分类号： G06F7/485 ,  G06F7/49947

摘要： A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.

摘要翻译： 一种用于对浮点操作数进行相加和相乘以产生固定大小的尾数结果的方法和装置。 根据本加法，第一浮点数操作数的尾数根据相对操作数指数信息移位。 接下来，将第一操作数尾数添加到第二操作数尾数。 所述添加步骤包括用随机生成的进位位替换第一操作数尾数的最不重要的非重叠部分。 根据乘法方法，从一对浮点运算符尾数生成部分乘积数组。 接下来，在将部分乘积阵列压缩为压缩尾数结果之前，将部分乘积阵列的低阶位部分替换为随机生成的进位值。

公开(公告)号：US07233998B2

公开(公告)日：2007-06-19

申请号：US09816004

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US06941335B2

公开(公告)日：2005-09-06

申请号：US09999135

申请日：2001-11-29

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Kevin Nowka ,  Steven Douglas Posluszny ,  Joel Abraham Silberman

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Kevin Nowka ,  Steven Douglas Posluszny ,  Joel Abraham Silberman

IPC分类号： G06F7/38 ,  G06F7/42 ,  G06F7/485 ,  G06F7/499 ,  G06F17/10

CPC分类号： G06F7/485 ,  G06F7/49947

摘要： A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.

公开(公告)号：US06924802B2

公开(公告)日：2005-08-02

申请号：US10242566

申请日：2002-09-12

申请人： Gordon Clyde Fossum ,  Harm Peter Hofstee ,  Barry L. Minor ,  Mark Richard Nutter

发明人： Gordon Clyde Fossum ,  Harm Peter Hofstee ,  Barry L. Minor ,  Mark Richard Nutter

IPC分类号： G06F17/17 ,  G06T11/20 ,  G06F15/76

CPC分类号： G06F17/17 ,  G06T11/203

摘要： A system, method, and computer program product are provided for generating display data. The data processing system loads coefficient values corresponding to a behavior of a selected function in pre-defined ranges of input data. The data processing system then determines, responsive to items of input data, the range of input data in which the selected function is to be estimated. The data processing system then selects, through the use of a vector permute function, the coefficient values, and evaluates an index function at the each of the items of input data. It then estimates the value of the selected function through parallel mathematical operations on the items of input data, the selected coefficient values, and the values of the index function, and, responsive to the one or more values of the selected function, generates display data.

摘要翻译： 提供了用于产生显示数据的系统，方法和计算机程序产品。 数据处理系统在预定义的输入数据范围内加载与选定功能的行为相对应的系数值。 然后，数据处理系统响应于输入数据的项目确定要在其中估计所选择的功能的输入数据的范围。 然后，数据处理系统通过使用向量置换函数来选择系数值，并且在输入数据的每一项上评估索引函数。 然后，通过对输入数据，所选系数值和索引函数的值的并行数学运算来估计所选函数的值，并且响应于所选函数的一个或多个值，生成显示数据 。

公开(公告)号：US06760819B2

公开(公告)日：2004-07-06

申请号：US09895888

申请日：2001-06-29

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty ,  Thuong Quang Truong

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty ,  Thuong Quang Truong

IPC分类号： G06F1208

CPC分类号： G06F12/0822 ,  G06F12/0811 ,  G06F12/084

摘要： A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced and more efficient snoop resolution and coherency operations with the processor caches are provided. A copy of the internal (L1) cache directory is provided within the lower level (L2) cache or memory. The snoop operations and coherency maintenance operations of the L1 directory are completed by comparing the snoop addresses with the address tags of the copy of the L1 directory in the L2 cache. Updates to the coherency states of the copy of the L1 directory are mirrored in the L1 directory and L1 cache. This eliminates the need for the individual coherency buses of each processor that is coupled to the L2 cache and speeds up coherency operations because the snoops do not have to be transmitted to the L1 caches.

摘要翻译： 提供具有共享低级高速缓存（或存储器）的多处理器数据处理系统中的处理器 - 高速缓存操作方案和拓扑，通过该共享低级高速缓存（或存储器）减少一致性总线的数量并且提供与处理器高速缓存更有效的窥探分辨率和一致性操作。 在低级（L2）高速缓存或内存中提供内部（L1）缓存目录的副本。 通过将侦听地址与L2缓存中L1目录的副本的地址标签进行比较，完成L1目录的侦听操作和一致性维护操作。 对L1目录的副本的一致性状态的更新被镜像在L1目录和L1缓存中。 这消除了对耦合到L2高速缓存的每个处理器的各个一致性总线的需要，并且加速一致性操作，因为该探测不必被传送到L1高速缓存。