公开(公告)号：US08796084B2

公开(公告)日：2014-08-05

申请号：US12776011

申请日：2010-05-07

申请人： Hung Chih Tsai ,  Chih Chieh Chen ,  Sheng Chen Chung ,  Kong Beng Thei ,  Harry Chuang

发明人： Hung Chih Tsai ,  Chih Chieh Chen ,  Sheng Chen Chung ,  Kong Beng Thei ,  Harry Chuang

IPC分类号： H01L21/8238 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L21/31144 ,  H01L21/823814 ,  H01L21/82385 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a semiconductor substrate, wherein the second gate is larger than the first gate. The first gate and second gate could be associated with silicon-germanium (SiGe) source and drain regions to form p-type transistors. Next, a photoresist layer is deposited, and an opening of the photoresist layer is formed on the hard mask of the second gate. Then, the photoresist layer on the first and second gates is removed completely by etching back. Because there is no photoresist residue, the hard masks on the first and second gates can be removed completely afterwards.

摘要翻译： 如下进行半导体制造工序中的门上去除硬掩模的方法。 首先，在半导体衬底上形成具有硬掩模的第一栅极和第二栅极，其中第二栅极大于第一栅极。 第一栅极和第二栅极可以与硅 - 锗（SiGe）源极和漏极区域相关联以形成p型晶体管。 接下来，沉积光致抗蚀剂层，并且在第二栅极的硬掩模上形成光致抗蚀剂层的开口。 然后，通过蚀刻完全去除第一和第二栅极上的光致抗蚀剂层。 因为没有光致抗蚀剂残留物，所以第一和第二栅极上的硬掩模可以被完全去除。

公开(公告)号：US08598630B2

公开(公告)日：2013-12-03

申请号：US12470333

申请日：2009-05-21

申请人： Gary Shen ,  Ming-Yuan Wu ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang

发明人： Gary Shen ,  Ming-Yuan Wu ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L23/52

CPC分类号： H01L23/544 ,  H01L21/31051 ,  H01L21/823828 ,  H01L23/585 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.

摘要翻译： 提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，第一和第二区域彼此隔离，形成在第一区域中的多个晶体管，形成在第二区域中的对准标记， 对准标记具有在第一方向上的多个有效区域，以及形成在所述对准标记上的伪栅极结构，所述伪栅极结构在与所述第一方向不同的第二方向上具有多条线。

公开(公告)号：US08552522B2

公开(公告)日：2013-10-08

申请号：US13151666

申请日：2011-06-02

申请人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

发明人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L21/70

CPC分类号： H01L21/76883 ,  H01L21/76229

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

公开(公告)号：US08461629B2

公开(公告)日：2013-06-11

申请号：US13178755

申请日：2011-07-08

申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

公开(公告)号：US08390072B2

公开(公告)日：2013-03-05

申请号：US13156558

申请日：2011-06-09

申请人： Harry Chuang ,  Kong-Beng Thei ,  Su-Chen Lai ,  Gary Shen

发明人： Harry Chuang ,  Kong-Beng Thei ,  Su-Chen Lai ,  Gary Shen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823828 ,  H01L21/31053 ,  H01L21/823437 ,  H01L29/66545 ,  Y10S438/926

摘要： A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.

摘要翻译： 提供了一种制造半导体器件的方法，其包括提供半导体衬底，形成多个晶体管，每个晶体管具有虚拟栅极结构，在包括虚拟栅极结构的衬底上形成接触蚀刻停止层（CESL），形成 第一电介质层，以填充相邻虚拟栅极结构之间的每个区域的一部分，在CESL和第一介电层上形成化学机械抛光（CMP）阻挡层，在CMP停止层上形成第二介电层，对CMP 所述第二电介质层在所述CMP停止层处基本上停止，并且执行过度抛光以暴露所述伪栅极结构。

公开(公告)号：US08372706B2

公开(公告)日：2013-02-12

申请号：US13218720

申请日：2011-08-26

申请人： Shun-Jang Liao ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Shun-Jang Liao ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Provided is a method of fabricating a semiconductor device. A first hard mask layer is formed on a substrate. A second hard mask layer s formed the substrate overlying the first hard mask layer. A dummy gate structure on the substrate is formed on the substrate by using at least one of the first and the second hard mask layers to pattern the dummy gate structure. A spacer element is formed adjacent the dummy gate structure. A strained region on the substrate adjacent the spacer element (e.g., abutting the spacer element). The second hard mask layer and the spacer element are then removed after forming the strained region.

摘要翻译： 提供一种制造半导体器件的方法。 在基板上形成第一硬掩模层。 第二硬掩模层形成覆盖在第一硬掩模层上的基板。 通过使用第一和第二硬掩模层中的至少一个来在衬底上形成伪栅极结构，以对虚拟栅极结构进行图案化。 在虚拟栅极结构附近形成间隔元件。 邻近衬垫元件的衬底上的应变区域（例如，邻接间隔元件）。 然后在形成应变区域之后去除第二硬掩模层和间隔元件。

公开(公告)号：US08361866B2

公开(公告)日：2013-01-29

申请号：US13204461

申请日：2011-08-05

申请人： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

发明人： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

IPC分类号： H01L21/8234

CPC分类号： H01L27/0883 ,  G11C11/412 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S438/919

摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

公开(公告)号：US08304839B2

公开(公告)日：2012-11-06

申请号：US13216114

申请日：2011-08-23

申请人： Kong-Beng Thei ,  Harry Chuang

发明人： Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L27/11

CPC分类号： H01L27/0629 ,  H01L23/5256 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Methods for fabricating a semiconductor device are disclosed. In an example, a method includes forming an isolation region on a substrate, wherein the isolation region extends a depth into the substrate from a substrate surface; forming a recess in the isolation region, wherein the recess is defined by a concave surface of the isolation region; and forming a first gate structure over the substrate surface and a second gate structure over the concave surface of the isolation region.

公开(公告)号：US20120225529A1

公开(公告)日：2012-09-06

申请号：US13465551

申请日：2012-05-07

申请人： Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

发明人： Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC分类号： H01L21/336 ,  H01L21/425

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US20120196434A1

公开(公告)日：2012-08-02

申请号：US13443550

申请日：2012-04-10

申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L21/02

CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

摘要翻译： 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。