Method for manufacturing a chip scale package having slits formed on a substrate

    公开(公告)号:US06432746B1

    公开(公告)日:2002-08-13

    申请号:US09840725

    申请日:2001-04-23

    IPC分类号: H01L2144

    摘要: A method for manufacturing a chip scale package (CSP) including a semiconductor chip and conductive bumps is disclosed. In the present invention, a flexible substrate is provided with a conductive pattern formed thereon. The substrate has a top surface and a bottom surface. Then, a first photosensitive resin pattern is formed over the top surface of the substrate. Next, the first photosensitive resin pattern is cured. Subsequently, a second photosensitive resin pattern is formed over the cured first photosensitive resin pattern. The second photosensitive resin pattern includes a slit comprising a bottom of the first photosensitive resin pattern and side walls of the second photosensitive resin pattern. With the present invention, the problem of burning of neighboring patterns as well as the problem of the overflow of the encapsulant can be overcome.