公开(公告)号：US09171827B2

公开(公告)日：2015-10-27

申请号：US14148717

申请日：2014-01-06

申请人： Jin-Ho Lee ,  Hee-Seok Lee ,  Se-Ho You ,  Jeong-Oh Ha

发明人： Jin-Ho Lee ,  Hee-Seok Lee ,  Se-Ho You ,  Jeong-Oh Ha

IPC分类号： H01L23/00 ,  H01L25/10 ,  H05K1/02 ,  H01L23/31 ,  H05K3/28

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13101 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13169 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45164 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45171 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48601 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48701 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48801 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/85401 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19106 ,  H05K1/0271 ,  H05K3/284 ,  H05K2201/09136 ,  H05K2201/09909 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stack type semiconductor package includes a lower semiconductor package including a lower package substrate and at least one lower semiconductor chip disposed on the lower package substrate; an upper semiconductor package including an upper package substrate larger than the lower package substrate and at least one upper semiconductor chip disposed on the upper package substrate; an inter-package connector connecting an upper surface of the lower package substrate to a lower surface of the upper package substrate; and a filler filling in between the lower package substrate and the upper package substrate while substantially surrounding the inter-package connector.

摘要翻译： 堆叠型半导体封装包括下半导体封装，其包括下封装衬底和布置在下封装衬底上的至少一个下半导体芯片; 上半导体封装，包括比下封装衬底大的上封装衬底和设置在上封装衬底上的至少一个上半导体芯片; 将所述下封装基板的上表面连接到所述上封装基板的下表面的封装间连接器; 以及填充在下封装衬底和上封装衬底之间的填料，同时基本上围绕封装间连接器。

公开(公告)号：US09165893B2

公开(公告)日：2015-10-20

申请号：US13229193

申请日：2011-09-09

申请人： Yong-Hoon Kim ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

发明人： Yong-Hoon Kim ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

IPC分类号： H04B5/00 ,  H01L23/64 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L23/645 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H04B5/0012 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0075 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

摘要翻译： 公开了一种包括通孔的半导体器件。 半导体器件可以包括第一半导体芯片，其包括形成在第一表面上的收发器电路，形成在与第一表面相对的第二表面上的第一耦合导体图案，以及连接收发器电路和第一耦合导电 模式。 可以存在位于第二半导体芯片上的收发器，并且包括面向与第一耦合导电图案无线通信的第一耦合导电图案的第二耦合导电图案。

公开(公告)号：US20140291868A1

公开(公告)日：2014-10-02

申请号：US14148717

申请日：2014-01-06

申请人： JIN-HO LEE ,  HEE-SEOK LEE ,  SE-HO YOU ,  JEONG-OH HA

发明人： JIN-HO LEE ,  HEE-SEOK LEE ,  SE-HO YOU ,  JEONG-OH HA

IPC分类号： H01L23/00

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13101 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13169 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45164 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45171 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48601 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48701 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48801 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/85401 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19106 ,  H05K1/0271 ,  H05K3/284 ,  H05K2201/09136 ,  H05K2201/09909 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stack type semiconductor package includes a lower semiconductor package including a lower package substrate and at least one lower semiconductor chip disposed on the lower package substrate; an upper semiconductor package including an upper package substrate larger than the lower package substrate and at least one upper semiconductor chip disposed on the upper package substrate; an inter-package connector connecting an upper surface of the lower package substrate to a lower surface of the upper package substrate; and a filler filling in between the lower package substrate and the upper package substrate while substantially surrounding the inter-package connector.

摘要翻译： 堆叠型半导体封装包括下半导体封装，其包括下封装衬底和设置在下封装衬底上的至少一个下半导体芯片; 上半导体封装，包括比下封装衬底大的上封装衬底和设置在上封装衬底上的至少一个上半导体芯片; 将所述下封装基板的上表面连接到所述上封装基板的下表面的封装间连接器; 以及填充在下封装基板和上封装基板之间的填料，同时基本上围绕封装间连接器。

公开(公告)号：US08552521B2

公开(公告)日：2013-10-08

申请号：US12639228

申请日：2009-12-16

申请人： Eun-seok Song ,  Hee-seok Lee ,  Sung-woo Park

发明人： Eun-seok Song ,  Hee-seok Lee ,  Sung-woo Park

IPC分类号： H01L29/00

CPC分类号： H01L23/66 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/19051 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package removes power noise by using a ground impedance. The semiconductor package includes an analog circuit block, a digital circuit block, an analog ground impedance structure, a digital ground impedance structure, and an integrated ground. The integrated ground and the analog circuit block are electrically connected via the analog ground impedance structure, and the integrated ground and the digital circuit block are electrically connected via the digital ground impedance structure, and an inductance of the analog ground impedance structure is greater than an inductance of the digital ground impedance structure.

摘要翻译： 半导体封装通过使用接地阻抗来消除功率噪声。 半导体封装包括模拟电路块，数字电路块，模拟地阻抗结构，数字接地阻抗结构和集成地。 集成地和模拟电路块通过模拟接地阻抗结构电连接，集成地和数字电路块通过数字接地阻抗结构电连接，模拟地阻抗结构的电感大于 数字接地阻抗结构的电感。

公开(公告)号：US08299597B2

公开(公告)日：2012-10-30

申请号：US12502324

申请日：2009-07-14

申请人： Yun-Seok Choi ,  Hee-Seok Lee

发明人： Yun-Seok Choi ,  Hee-Seok Lee

IPC分类号： H01L23/48

CPC分类号： H01L23/4985 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/60 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor chip can include a semiconductor substrate, an input portion and an output portion. A circuit element can be formed in the semiconductor substrate. The input portion can be formed on the semiconductor substrate. The input portion can include a first input pad to receive an input signal from the outside and a second input pad spaced apart from the first input pad, the second input pad being electrically connected to the first input pad through an external connection line such that the second input pad inputs the input signal to the circuit element. The output portion can be formed on the semiconductor substrate. The output pad can include an output pad to output an output signal from the circuit element.

摘要翻译： 半导体芯片可以包括半导体衬底，输入部分和输出部分。 电路元件可以形成在半导体衬底中。 输入部分可以形成在半导体衬底上。 输入部分可以包括用于从外部接收输入信号的第一输入焊盘和与第一输入焊盘间隔开的第二输入焊盘，第二输入焊盘通过外部连接线电连接到第一输入焊盘，使得 第二输入焊盘将输入信号输入到电路元件。 输出部分可以形成在半导体衬底上。 输出焊盘可以包括输出焊盘以输出来自电路元件的输出信号。

公开(公告)号：US20120105089A1

公开(公告)日：2012-05-03

申请号：US13348767

申请日：2012-01-12

申请人： Eun-seok SONG ,  Dong-han KIM ,  Hee-seok LEE

发明人： Eun-seok SONG ,  Dong-han KIM ,  Hee-seok LEE

IPC分类号： G01R1/067 ,  G01R31/26

CPC分类号： G01R31/2884 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

摘要翻译： 公开了半导体封装和测试方法。 封装包括具有顶表面和底表面的衬底，安装在衬底的位于中心的半导体芯片安装区域中的半导体芯片以及设置在衬底的顶表面和底表面上的多个测试焊盘，并且包括第一组测试焊盘 配置在衬底的顶表面和底表面上并且具有在衬底的相应顶部和底部表面上方的第一高度，以及设置在衬底的下表面上并具有大于第一衬底的第二高度的第二组测试焊盘 其中第二组测试垫中的每一个包括附接到其上的焊球。

公开(公告)号：US20110316119A1

公开(公告)日：2011-12-29

申请号：US13168111

申请日：2011-06-24

申请人： Yong-hoon KIM ,  Yeong-jun Cho ,  Ji-hyun Lee ,  Hee-seok Lee

发明人： Yong-hoon KIM ,  Yeong-jun Cho ,  Ji-hyun Lee ,  Hee-seok Lee

IPC分类号： H01L23/485

CPC分类号： H01G4/30 ,  H01G2/065 ,  H01G4/228 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/642 ,  H01L24/16 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01038 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1902 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Provided is a semiconductor package including a de-coupling capacitor. The semiconductor package includes a substrate, on an upper surface of which a semiconductor chip is mounted; a plurality of first conductive bumps that are disposed on a lower surface of the substrate and that electrically connect the substrate to an external device; and a de-coupling capacitor that is disposed on the lower surface of the substrate and includes an electrode portion and at least one dielectric layer, wherein the electrode portion of the de-coupling capacitor includes second conductive bumps that electrically connect the substrate to an external device.

摘要翻译： 提供了包括去耦电容器的半导体封装。 半导体封装包括：衬底，其上表面安装有半导体芯片; 多个第一导电凸块，其设置在所述基板的下表面上，并将所述基板电连接到外部装置; 以及解耦电容器，其设置在所述基板的下表面上并且包括电极部分和至少一个电介质层，其中所述解耦电容器的电极部分包括将所述基板电连接到外部的第二导电凸块 设备。

公开(公告)号：US20110304763A1

公开(公告)日：2011-12-15

申请号：US13095155

申请日：2011-04-27

申请人： Mi-Na Choi ,  Kyoung-Sei Choi ,  Hee-Seok Lee ,  Yong-Hoon Kim ,  Hee-Jung Hwang ,  Se-Ran Bae

发明人： Mi-Na Choi ,  Kyoung-Sei Choi ,  Hee-Seok Lee ,  Yong-Hoon Kim ,  Hee-Jung Hwang ,  Se-Ran Bae

IPC分类号： H04N5/225 ,  H01L31/0216

CPC分类号： H04N5/2253

摘要： An image sensor chip, a camera module, and devices incorporating the image sensor chip and camera module include a light receiving unit on which light is incident, a logic unit provided to surround the light receiving unit, and an electromagnetic wave shielding layer formed on the logic unit and not formed on the light receiving unit.

摘要翻译： 图像传感器芯片，相机模块以及包含图像传感器芯片和相机模块的装置包括光入射的光接收单元，围绕光接收单元的逻辑单元和形成在该光接收单元上的电磁波屏蔽层 逻辑单元，并且不形成在光接收单元上。

公开(公告)号：US20110227221A1

公开(公告)日：2011-09-22

申请号：US13028836

申请日：2011-02-16

申请人： Ji-Yong Park ,  Hee-Seok Lee ,  Chul-Woo Kim ,  Sang-Gui Jo ,  Kwang-Jin Bae ,  Seung-Hwan Kim

发明人： Ji-Yong Park ,  Hee-Seok Lee ,  Chul-Woo Kim ,  Sang-Gui Jo ,  Kwang-Jin Bae ,  Seung-Hwan Kim

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L24/03 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/1403 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/05552 ,  H01L2924/00

摘要： An electronic device includes first and second interconnections formed on a first surface of a substrate and spaced apart from each other. The electronic device includes a first insulating material layer disposed on the substrate including the first and second interconnections and including a first opening exposing a predetermined region of the first interconnection. The electronic device further includes a first pad filling the first opening and having a greater width than the first opening. The first pad covers at least a part of the second interconnection adjacent to one end of the first interconnection, and the first pad is electrically insulated from the second interconnection by the first insulating material layer.

摘要翻译： 电子设备包括形成在基板的第一表面上并彼此间隔开的第一和第二互连。 电子设备包括设置在基板上的第一绝缘材料层，包括第一和第二互连，并且包括暴露第一互连的预定区域的第一开口。 电子设备还包括填充第一开口并且具有比第一开口更大的宽度的第一垫。 第一焊盘覆盖与第一互连的一端相邻的第二互连的至少一部分，并且第一焊盘通过第一绝缘材料层与第二互连电绝缘。

公开(公告)号：US07936232B2

公开(公告)日：2011-05-03

申请号：US12824415

申请日：2010-06-28

申请人： Eun-seok Song ,  Hee-seok Lee ,  So-young Lim

发明人： Eun-seok Song ,  Hee-seok Lee ,  So-young Lim

IPC分类号： H04B3/28

CPC分类号： H01Q15/006

摘要： A substrate for a semiconductor package includes a dielectric substrate, a circuit pattern formed on a first surface of the dielectric substrate, and an electromagnetic band gap (EGB) pattern. The EGB pattern includes multiple unit structures formed on a second surface of the dielectric substrate, where each unit structure includes a flat conductor electrically connected to the circuit pattern through a ground connection, and multiple spiral-patterned conductors electrically connected to the flat conductor. The second surface is formed on an opposite side of the dielectric substrate from the first surface. Each flat conductor is electrically connected to a flat conductor of another one of the unit structures. At least one of the spiral-patterned conductors in each one of the unit structures is electrically connected to another one of the spiral-patterned conductors.

摘要翻译： 用于半导体封装的衬底包括电介质衬底，形成在电介质衬底的第一表面上的电路图案和电磁带隙（EGB）图案。 EGB图案包括形成在电介质基板的第二表面上的多个单元结构，其中每个单元结构包括通过接地连接电连接到电路图案的扁平导体，以及电连接到扁平导体的多个螺旋图案导体。 第二表面形成在电介质基板的与第一表面相反的一侧上。 每个扁平导体电连接到另一个单元结构的扁平导体。 每个单元结构中的至少一个螺旋图案导体电连接到另一个螺旋图案导体。