公开(公告)号：US09977170B2

公开(公告)日：2018-05-22

申请号：US14713026

申请日：2015-05-15

申请人： Heon Cheol Kim

发明人： Heon Cheol Kim ,  Jang Hwan Hwang

IPC分类号： G02B6/26 ,  F21V8/00 ,  G02B1/04 ,  G02B3/08

CPC分类号： G02B6/001 ,  G02B1/041 ,  G02B1/048 ,  G02B3/08 ,  G02B6/00 ,  G02B6/0006 ,  G02B6/0008 ,  C08L69/00 ,  C08L33/10 ,  C08L75/04

摘要： A light device using a light cylinder is disclosed. The light device includes a cover, a light source section combined with at least part of an inside surface of the cover and configured to output a light, and a light cylinder configured to include one entrance part and a plurality of output parts. The entrance part is combined with the light source section, and the light incident through the entrance part is outputted through the output parts.

公开(公告)号：US06338154B2

公开(公告)日：2002-01-08

申请号：US09060242

申请日：1998-04-14

申请人： Heon-cheol Kim

发明人： Heon-cheol Kim

IPC分类号： G01R3128

CPC分类号： G11C29/20

摘要： A memory address generating apparatus and method of a dynamic memory testing circuit for generating addresses for testing a dynamic memory which uses all the available addresses of the dynamic memory, which does not use the most significant addresses, and which does not use middle addresses among all the available addresses are provided. The address generator can obtain an up-counted address by up counting the addresses used by the dynamic memory. It can obtain a down-counted address by inverting the N-bit up-counted value, or by subtracting the N-bit up-counted value from the maximum address, or by combining the inverted MSB portion of the N-bit up-counted value with the LSB portion of the N-bit up-counted value subtracted from the LSB portion of the maximum address used in the dynamic memory. The down and up counted addresses are used as addresses for selectively testing the dynamic memory according to a selected testing method.

摘要翻译： 一种用于生成用于测试动态存储器的地址的动态存储器测试电路的存储器地址产生装置和方法，该动态存储器使用不使用最高有效地址的动态存储器的所有可用地址，并且不使用所有 提供可用的地址。 地址生成器可以通过对动态存储器使用的地址进行计数来获得递增计数的地址。 它可以通过反转N位向上计数值，或从最大地址减去N位向上计数值，或通过组合N位向上计数的反相MSB部分来获得递减计数的地址 从动态存储器中使用的最大地址的LSB部分中减去N位向上计数值的LSB部分的值。 根据所选择的测试方法，将向下和向上计数的地址用作有选择地测试动态存储器的地址。

公开(公告)号：US6148426A

公开(公告)日：2000-11-14

申请号：US67671

申请日：1998-04-28

申请人： Heon-cheol Kim ,  Hong-shin Jun

发明人： Heon-cheol Kim ,  Hong-shin Jun

IPC分类号： G01R31/28 ,  G01R31/26 ,  G11C11/413 ,  G11C29/12 ,  G11C29/20

CPC分类号： G11C29/20

摘要： A memory address generator having a small chip area, a method for generating a memory address and a SRAM built-in self test (BIST) circuit using the same are described. When the number of addresses of a memory to be tested is 2.sup.n, where n is the number of bits in an address, the address generator includes an up counter for generating a first address of a series of sequentially increasing addresses, and an inverter for inverting the first address to generate a second address of a series of sequentially decreasing addresses. The address generator also includes a selector for selecting one of the first and second addresses, in response to a control signal, to output the selected address as an address of the memory. When the number of addresses of the memory to be tested is not 2.sup.n, the address generator includes an up counter for generating a first address of a series of sequentially increasing addresses up to a maximum address of the memory and a subtracter for subtracting the first address from the maximum address to generate a second address of a series of sequentially decreasing addresses. The address generator also includes a selector for selecting one of the first and second addresses, in response to control signal, to output the selected address as an address of the memory.

摘要翻译： 描述了具有小芯片面积的存储器地址发生器，用于产生存储器地址的方法和使用其的SRAM内置自测试（BIST）电路。 当要测试的存储器的地址数为2n时，其中n是地址中的位数，地址生成器包括用于产生一系列顺序增加地址的第一地址的上计数器，以及用于反转的反相器 所述第一地址生成一系列顺序减少的地址的第二地址。 地址生成器还包括用于响应于控制信号选择第一和第二地址之一的选择器，以将所选择的地址输出为存储器的地址。 当要测试的存储器的地址数不是2n时，地址生成器包括用于产生直到存储器的最大地址的一系列顺序增加的地址的第一地址的增加计数器和用于减去第一地址的减法器 从最大地址生成一系列顺序递减的地址的第二地址。 地址生成器还包括用于响应于控制信号选择第一和第二地址之一的选择器，以将所选择的地址输出为存储器的地址。

公开(公告)号：US5754758A

公开(公告)日：1998-05-19

申请号：US638372

申请日：1996-04-26

申请人： Sang-Hyeon Baeg ,  Heon-cheol Kim ,  Ho-royng Kim ,  Chang-hyun Cho

发明人： Sang-Hyeon Baeg ,  Heon-cheol Kim ,  Ho-royng Kim ,  Chang-hyun Cho

IPC分类号： G06F12/16 ,  G06F13/00 ,  G11C29/32 ,  G01R31/28 ,  G06F11/22

CPC分类号： G11C29/32

摘要： A serial memory interface includes a register having a plurality of flip-flops forming a scan chain and coupled to both the input and output terminals of memory cells. An interlaced scan is established by interconnecting scan chains between multiple memory blocks. The interface structure provides a means for efficiently performing a built-in self test of an embedded memory while requiring minimal overhead in hardware structure.

摘要翻译： 串行存储器接口包括具有形成扫描链并耦合到存储器单元的输入和输出端的多个触发器的寄存器。 通过在多个存储器块之间互连扫描链来建立隔行扫描。 接口结构提供了一种有效地执行嵌入式存储器的内置自检的方式，同时在硬件结构中需要最小的开销。

公开(公告)号：US5844914A

公开(公告)日：1998-12-01

申请号：US850807

申请日：1997-05-02

申请人： Heon-Cheol Kim ,  Hong-Sin Jun ,  Chang-Hyun Cho

发明人： Heon-Cheol Kim ,  Hong-Sin Jun ,  Chang-Hyun Cho

IPC分类号： G11C11/401 ,  G01R31/28 ,  G01R31/3181 ,  G11C11/406 ,  G11C29/08 ,  G11C29/12 ,  G11C29/18 ,  G06F11/00

CPC分类号： G11C29/18 ,  G01R31/31813

摘要： A semiconductor memory device and method is shown in which a built-in system test (BIST) circuit determines, based upon the test algorithm and the refresh requirements of a DRAM memory cell array, a refresh point address where the BIST circuit performs a refresh operation on the test data in the memory cell array when the test address reaches the refresh point address. Another embodiment of a semiconductor memory device and method is also shown in which a BIST circuit descrambles the test address and test data before input to a memory circuit which includes address and data scrambling circuits such that the logical test address and test data generated according to a test algorithm matches the physical address and data in the memory cell array.

摘要翻译： 示出了半导体存储器件和方法，其中内置系统测试（BIST）电路基于测试算法和DRAM存储单元阵列的刷新要求确定BIST电路执行刷新操作的刷新点地址 当测试地址到达刷新点地址时，在存储单元阵列中的测试数据。 还示出了半导体存储器件和方法的另一实施例，其中BIST电路在输入到存储器电路之前对测试地址和测试数据进行解扰，该存储器电路包括地址和数据加扰电路，使得逻辑测试地址和根据 测试算法与存储单元阵列中的物理地址和数据相匹配。

公开(公告)号：US5938784A

公开(公告)日：1999-08-17

申请号：US951189

申请日：1997-10-15

申请人： Heon-Cheol Kim

发明人： Heon-Cheol Kim

IPC分类号： G06F7/00 ,  G01R3/00 ,  G01R31/3181 ,  G06F11/22 ,  G11C19/00 ,  G11C29/00 ,  G11C29/12 ,  G01R31/28

CPC分类号： G01R31/31813

摘要： A built-in self test (BIST) circuit using a linear feedback shift register (LFSR) and a multiple input signature register (MISR) requiring reduced circuitry exclusive of the number of inputs and outputs of the circuit to be tested. The BIST circuit is built in a prescribed circuit having a memory to test a target circuit in the prescribed circuit. The BIST circuit includes an LFSR, including a first logic section which is composed of a plurality of XOR gates and selection sections, and a first memory which is a part of the memory, for performing a primitive polynomial, an MISR, including a second logic section which is composed of a plurality of XOR gates and selection sections, and a second memory which is a part of the memory, for performing the primitive polynomial, and a BIST control section for controlling data input/output between the first and second memories and the target circuit and providing selection signals for controlling the selection sections in the first and second logic sections, the BIST control section controlling the target circuit and comparing operation results of the target circuit to perform the test of the target circuit.

摘要翻译： 使用线性反馈移位寄存器（LFSR）和多输入签名寄存器（MISR）的内置自检（BIST）电路，需要减少电路，不包括待测电路的输入和输出数量。 BIST电路内置在具有用于测试规定电路中的目标电路的存储器的规定电路中。 BIST电路包括LFSR，其包括由多个XOR门和选择部分组成的第一逻辑部分和作为存储器的一部分的第一存储器，用于执行原始多项式，MISR包括第二逻辑 由多个XOR门和选择部分组成的部分，以及作为存储器的一部分的第二存储器，用于执行原始多项式;以及BIST控制部分，用于控制第一和第二存储器之间的数据输入/输出; 目标电路并提供用于控制第一和第二逻辑部分中的选择部分的选择信号，BIST控制部分控制目标电路并比较目标电路的运行结果以执行目标电路的测试。

公开(公告)号：US20160282534A1

公开(公告)日：2016-09-29

申请号：US14713026

申请日：2015-05-15

申请人： Heon Cheol Kim

发明人： Heon Cheol Kim ,  Jang Hwan Hwang

IPC分类号： F21V8/00 ,  G02B1/04

CPC分类号： G02B6/001 ,  G02B1/041 ,  G02B1/048 ,  G02B3/08 ,  G02B6/00 ,  G02B6/0006 ,  G02B6/0008 ,  C08L69/00 ,  C08L33/10 ,  C08L75/04

摘要： A light device using a light cylinder is disclosed. The light device includes a cover, a light source section combined with one or more sides of inside sides of the cover and configured to output a light, and a light cylinder configured to include one entrance part and plural output parts. Here, the entrance part is combined with the light source section, and the light incident through the entrance part is outputted through the output parts.

摘要翻译： 公开了一种使用光筒的灯装置。 光装置包括盖，与盖的内侧的一侧或多侧相结合并被配置为输出光的光源部，以及配置成包括一个入口部和多个输出部的光筒。 这里，入射部与光源部组合，通过入射部入射的光通过输出部输出。

公开(公告)号：US06553530B1

公开(公告)日：2003-04-22

申请号：US09366252

申请日：1999-08-03

申请人： Heon-cheol Kim

发明人： Heon-cheol Kim

IPC分类号： G06F1100

CPC分类号： G01R31/31813 ,  G06F2201/83

摘要： Integrated circuit devices have a self-test capability in which a sequence of input data patterns are generated by a test pattern unit and are selectively applied to a functional or test block that is selected from a plurality of potential test blocks. The output data patterns that are generated by the selected test block are provided to a data compression unit that generates a signature in response thereto. This signature can then be compared with an expected pattern to determine whether the selected test block is functioning properly. Because the test pattern unit and the data compression unit are shared by a plurality of test blocks, the area normally reserved for test circuitry in an integrated circuit device can be reduced.

摘要翻译： 集成电路装置具有自检能力，其中输入数据模式序列由测试图案单元生成，并且被选择性地应用于从多个潜在测试块中选择的功能或测试块。 由所选择的测试块生成的输出数据模式被提供给响应于此生成签名的数据压缩单元。 然后可以将该签名与预期模式进行比较，以确定所选择的测试块是否正常工作。 由于测试图案单元和数据压缩单元由多个测试块共享，因此可以减少通常为集成电路设备中的测试电路预留的区域。

公开(公告)号：US06769084B2

公开(公告)日：2004-07-27

申请号：US09805431

申请日：2001-03-13

申请人： Heon Cheol Kim ,  Jin-Young Park

发明人： Heon Cheol Kim ,  Jin-Young Park

IPC分类号： G06F1100

CPC分类号： G11C29/20

摘要： A built-in self test (BIST) circuit and method is provided for testing semiconductor memory. A linear feedback shift register (LFSR) is used for addressing the memory locations to be tested. Test data is derived at least partially from the address data generated from the linear feedback shift register.

摘要翻译： 提供内置自检（BIST）电路和方法来测试半导体存储器。 线性反馈移位寄存器（LFSR）用于寻址要测试的存储单元。 至少部分地从线性反馈移位寄存器产生的地址数据导出测试数据。

公开(公告)号：US06574757B1

公开(公告)日：2003-06-03

申请号：US09566346

申请日：2000-05-08

申请人： Jin-Young Park ,  Heon-Cheol Kim

发明人： Jin-Young Park ,  Heon-Cheol Kim

IPC分类号： G11C2900

CPC分类号： G11C29/72 ,  G11C29/44 ,  G11C29/4401

摘要： An integrated circuit semiconductor device comprises a built-in self-repair (BISR) circuit including a plurality of row fill entries and a plurality of column fill entries for storing faulty memory cell information of an embedded memory. Sizes of the row and column fill entries are determined by the numbers of row and column redundancies of the embedded memory. The row/column fill entries store row/column addresses of the faulty memory cells, and the number of the faulty memory cells occurring at the same row/column address, respectively. In addition, the row/column fill entries include pointers for indicating opposite entries storing the column/row address corresponding to the row/column address. For repairing the faulty memory cells with the row and column redundancies, the BISR circuit selects row/column fill entries and deletes the number of the fault memory cells stored in the opposite fill entry. Thus, the information is deleted from the row/column fill entries with the exception of information to be repaired. Therefore, the self-repair of the faulty memory cells can be performed in the BISR circuit in response to the remaining information.

摘要翻译： 集成电路半导体器件包括内置的自修复（BISR）电路，其包括多个行填充条目和用于存储嵌入式存储器的有缺陷的存储器单元信息的多个列填充条目。 行和列填充条目的大小由嵌入式存储器的行和列冗余数决定。 行/列填充条目分别存储故障存储器单元的行/列地址以及在相同行/列地址处发生的故障存储器单元的数量。 此外，行/列填充条目包括用于指示存储与行/列地址相对应的列/行地址的相反条目的指针。 为了修复具有行和列冗余的故障存储单元，BISR电路选择行/列填充条目，并删除存储在相反填充条目中的故障存储单元的数量。 因此，除了要修复的信息之外，信息将从行/列填充条目中删除。 因此，可以在BISR电路中响应于剩余的信息来执行故障存储器单元的自修复。