公开(公告)号：US07969796B2

公开(公告)日：2011-06-28

申请号：US12007721

申请日：2008-01-15

申请人： Sang-hyuk Kwon ,  Hi-choon Lee

发明人： Sang-hyuk Kwon ,  Hi-choon Lee

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C11/406 ,  G11C11/4074

摘要： A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to count the pulse signal and sequentially output a plurality of selection signals. The plurality of transmitters may be configured to be sequentially enabled in response to individual selection signals of the plurality of selection signals to transmit the pulse signal. The plurality of pumpers may correspond to the plurality of transmitters. Each of the plurality of pumpers may be configured to collectively generate a high voltage based on the transmitted pulse signal from a corresponding transmitter of the plurality of transmitters.

摘要翻译： 高压发生电路可以包括脉冲信号发生器，计数器，多个发射器和/或多个泵器。 脉冲信号发生器可以被配置为响应于刷新命令信号被使能以输出脉冲信号。 计数器可以被配置为对脉冲信号进行计数并顺序地输出多个选择信号。 多个发射机可以被配置为响应于多个选择信号的各个选择信号而被顺序启用以发送脉冲信号。 多个泵器可以对应于多个发射器。 多个泵器中的每一个可以被配置为基于来自多个发射器的相应发射器的所发射的脉冲信号共同地产生高电压。

公开(公告)号：US20100109760A1

公开(公告)日：2010-05-06

申请号：US12610601

申请日：2009-11-02

申请人： Jeong Sik NAM ,  Hi Choon LEE

发明人： Jeong Sik NAM ,  Hi Choon LEE

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  G11C5/145

摘要： A voltage boosting circuit includes a first voltage boosting circuit configured to receive an external power supply voltage, and pump the external power supply voltage to a second boosting voltage higher than the external supply voltage in a single pumping stage, and a second voltage boosting circuit configured to receive the second boosting voltage and pump the second boosting voltage to a first boosting voltage higher than the second boosting voltage in two pumping stages.

摘要翻译： 升压电路包括：第一升压电路，被配置为接收外部电源电压，并且在单个泵浦级中将外部电源电压泵送到高于外部电源电压的第二升压电压;以及配置的第二升压电路 以在两个泵送级中接收第二升压电压并将第二升压电压泵送到高于第二升压电压的第一升压电压。

公开(公告)号：US20080170446A1

公开(公告)日：2008-07-17

申请号：US12007721

申请日：2008-01-15

申请人： Sang-hyuk Kwon ,  Hi-choon Lee

发明人： Sang-hyuk Kwon ,  Hi-choon Lee

IPC分类号： G11C5/14 ,  G05F3/02

CPC分类号： G11C5/147 ,  G11C11/406 ,  G11C11/4074

摘要： A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to count the pulse signal and sequentially output a plurality of selection signals. The plurality of transmitters may be configured to be sequentially enabled in response to individual selection signals of the plurality of selection signals to transmit the pulse signal. The plurality of pumpers may correspond to the plurality of transmitters. Each of the plurality of pumpers may be configured to collectively generate a high voltage based on the transmitted pulse signal from a corresponding transmitter of the plurality of transmitters.

摘要翻译： 高压发生电路可以包括脉冲信号发生器，计数器，多个发射器和/或多个泵器。 脉冲信号发生器可以被配置为响应于刷新命令信号被使能以输出脉冲信号。 计数器可以被配置为对脉冲信号进行计数并顺序地输出多个选择信号。 多个发射机可以被配置为响应于多个选择信号的各个选择信号而被顺序启用以发送脉冲信号。 多个泵器可以对应于多个发射器。 多个泵器中的每一个可以被配置为基于来自多个发射器的相应发射器的所发射的脉冲信号共同地产生高电压。

公开(公告)号：US20080046788A1

公开(公告)日：2008-02-21

申请号：US11561023

申请日：2006-11-17

申请人： Hi-Choon Lee ,  Sung-Bum Cho

发明人： Hi-Choon Lee ,  Sung-Bum Cho

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C29/1201 ,  G11C2029/2602

摘要： The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from an external portion for simultaneously selecting all of the plurality of memory regions during a test read operation, a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation, a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal during the test read operation, and a test control signal generating portion for comparing the test pattern data read from the plurality of memory regions to generate the output control signal for conditionally outputting the test pattern data as the test status data during the test read operation.

摘要翻译： 本发明提供一种包括存储单元阵列的半导体存储器件，该存储单元阵列包括多个存储区域，地址解码部分，用于解码从外部部分施加的地址，用于在测试读取操作期间同时选择所有多个存储器区域; 数据IO控制部分，用于在测试写入操作期间接收测试图案数据并将测试图案数据写入到多个存储器区域中的每一个，并且从多个存储区域中的一个读取测试图案数据，并在 测试读取操作，用于从外部部分接收测试图案数据并在测试写入操作期间将测试图案数据应用于数据IO控制部分的数据IO部分，以及从数据IO控制部分输出的测试图案数据 并响应于外部条件将测试图形数据作为测试状态数据输出到外部部分 在测试读取操作期间放置控制信号，以及测试控制信号生成部分，用于比较从多个存储区域读取的测试图形数据，以产生输出控制信号，用于有条件地输出测试模式数据作为测试状态数据 读操作。

公开(公告)号：US20070165470A1

公开(公告)日：2007-07-19

申请号：US11651973

申请日：2007-01-11

申请人： Jin-Hyung Cho ,  Hi-Choon Lee

发明人： Jin-Hyung Cho ,  Hi-Choon Lee

IPC分类号： G11C29/00

CPC分类号： G11C29/12 ,  G01R31/3004 ,  G11C29/006 ,  G11C29/12005 ,  G11C2029/1204

摘要： A semiconductor device for generating a test voltage for a wafer burn-in test and method thereof is disclosed. To generate the test voltage for a wafer burn-in test, a control signal may be generated in response to a supply voltage from an external wafer burn-in test device. A supplementary voltage may be generated in response to the control signal by using an internal voltage driving circuit. The test voltage may be generated by combining the supply voltage and the supplementary voltage.

摘要翻译： 公开了一种用于生成晶片老化测试的测试电压的半导体器件及其方法。 为了产生用于晶片老化测试的测试电压，可以响应于来自外部晶片老化测试装置的电源电压而产生控制信号。 可以通过使用内部电压驱动电路来响应于控制信号产生辅助电压。 可以通过组合电源电压和辅助电压来产生测试电压。

公开(公告)号：US06798703B2

公开(公告)日：2004-09-28

申请号：US10348752

申请日：2003-01-23

申请人： Hi-choon Lee

发明人： Hi-choon Lee

IPC分类号： G11C700

CPC分类号： G11C29/808

摘要： A semiconductor memory device that efficiently replaces defective word lines by redundancy word lines. The semiconductor memory device includes a plurality of banks, each bank having a plurality of normal word lines and a plurality of redundancy word lines. A defective word line can be replaced by the redundancy word lines when defects occur in the normal word lines. When word line defects occur, redundancy word lines banks adjacent to the bank having the defective work lines may be used.

摘要翻译： 一种半导体存储器件，其通过冗余字线有效地代替有缺陷的字线。 半导体存储器件包括多个存储体，每个存储体具有多个正常字线和多个冗余字线。 当正常字线中出现缺陷时，可以用冗余字线代替有缺陷的字线。 当发生字线缺陷时，可以使用与具有缺陷工作线的组相邻的冗余字线。

公开(公告)号：US20110235441A1

公开(公告)日：2011-09-29

申请号：US13067404

申请日：2011-05-31

申请人： Sang-hyuk Kwon ,  Hi-choon Lee

发明人： Sang-hyuk Kwon ,  Hi-choon Lee

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C11/406 ,  G11C11/4074

摘要： A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to count the pulse signal and sequentially output a plurality of selection signals. The plurality of transmitters may be configured to be sequentially enabled in response to individual selection signals of the plurality of selection signals to transmit the pulse signal. The plurality of pumpers may correspond to the plurality of transmitters. Each of the plurality of pumpers may be configured to collectively generate a high voltage based on the transmitted pulse signal from a corresponding transmitter of the plurality of transmitters.

公开(公告)号：US07800961B2

公开(公告)日：2010-09-21

申请号：US12260206

申请日：2008-10-29

申请人： Chris Ji Yoon Son ,  Hi-Choon Lee

发明人： Chris Ji Yoon Son ,  Hi-Choon Lee

IPC分类号： G11C16/04

CPC分类号： G11C8/08 ,  G11C11/406 ,  G11C11/4087 ,  G11C2211/4065 ,  G11C2211/4067

摘要： A word line driver for use in a semiconductor memory device includes a boosted voltage generator, a sub word line driver and a main word line driver. The boosted voltage generator generates a boosted voltage by receiving an internal power supply voltage and pumping electric charge. The sub word line driver receives the internal power supply voltage and activates a boosted voltage control signal after supplying the internal power supply voltage to a boost node in a command operating mode. The main word line driver enables a word line by supplying the boosted voltage to the boost node in response to the boosted voltage control signal in a normal operating mode, and enables the word line with the boosted voltage after boosting the word line to the internal power supply voltage by changing the boost node from the internal power supply voltage to the boosted voltage in the command operating mode.

摘要翻译： 用于半导体存储器件的字线驱动器包括升压电压发生器，子字线驱动器和主字线驱动器。 升压电压发生器通过接收内部电源电压和泵送电荷而产生升压电压。 子字线驱动器接收内部电源电压，并且在命令操作模式下将内部电源电压提供给升压节点之后激活升压电压控制信号。 主字符驱动器通过在正常工作模式下响应于升压电压控制信号而将升压电压提供给升压节点来实现字线，并且在将字线升压到内部电源之后使得具有升压电压的字线 在指令运行模式下，通过将升压节点从内部电源电压改变为升压电压来提供电压。

公开(公告)号：US20090003104A1

公开(公告)日：2009-01-01

申请号：US12155512

申请日：2008-06-05

申请人： Hi-Choon LEE

发明人： Hi-Choon LEE

IPC分类号： G11C29/00

CPC分类号： G11C29/26 ,  G11C2029/1202

摘要： A test circuit and method for use in a semiconductor memory device is provided. The test method for use in a semiconductor memory device including a plurality of memory blocks may include sequentially enabling a plurality of word lines by applying a stress to the wordlines and performing a test operation, in response to sequentially applied test addresses, each of the word lines being sequentially selected from the plurality of memory blocks and enabled.

摘要翻译： 提供了一种用于半导体存储器件的测试电路和方法。 在包括多个存储块的半导体存储器件中使用的测试方法可以包括通过对字线施加应力并且响应于顺序施加的测试地址来执行测试操作来顺序启用多个字线，每个字 从多个存储器块顺序选择并使能。

公开(公告)号：US20080111593A1

公开(公告)日：2008-05-15

申请号：US11819608

申请日：2007-06-28

申请人： Sung-Yub Jang ,  Hi-Choon Lee

发明人： Sung-Yub Jang ,  Hi-Choon Lee

IPC分类号： H03K3/00 ,  H03L7/00

CPC分类号： G06F1/24 ,  H03K17/223

摘要： A power-up reset circuit includes a sensing circuit and an output circuit. The sensing circuit outputs a node voltage in response to an external power supply voltage. The output circuit outputs a voltage sensing signal in response to the node voltage. A signal generation circuit outputs a reset signal in response to the voltage sensing signal. A first resistance adjustment circuit adjusts the level of the node voltage in response to an externally input first control signal. A second resistance adjustment circuit adjusts the level of the voltage sensing signal in response to an externally input second control signal.

摘要翻译： 上电复位电路包括感测电路和输出电路。 感测电路响应于外部电源电压输出节点电压。 输出电路响应于节点电压输出电压感测信号。 信号发生电路响应于电压感测信号输出复位信号。 第一电阻调节电路响应于外部输入的第一控制信号来调节节点电压的电平。 第二电阻调节电路响应于外部输入的第二控制信号来调节电压感测信号的电平。