公开(公告)号：US20070085595A1

公开(公告)日：2007-04-19

申请号：US10576292

申请日：2004-10-08

申请人： Masato Taki ,  Hideki Tojima

发明人： Masato Taki ,  Hideki Tojima

IPC分类号： H03K3/01

CPC分类号： H01L29/7816 ,  H01L27/092 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7824 ,  H01L29/7835

摘要： A semiconductor apparatus (100) comprises a low potential reference circuit region (1) and a high potential reference circuit region (2), and the high potential reference circuit region (2) is surrounded by a high withstand voltage separating region (3). By a trench (4) formed in the outer periphery of the high withstand voltage separating region (3), the low potential reference circuit region (1) and high potential reference circuit region (2) are separated from each other. Further, the trench (4) is filled up with an insulating material, and insulates the low potential reference circuit region (1) and high potential reference circuit region (2). The high withstand voltage separating region (3) is partitioned by the trench (4), high withstand voltage NMOS (5) or high withstand voltage PMOS (6) is provided in the partitioned position.

摘要翻译： 半导体装置（100）包括低电位基准电路区域（1）和高电位基准电路区域（2），高电位基准电路区域（2）由高耐压分离区域（3）包围。 通过形成在高耐压分离区域（3）的外周的沟槽（4），低电位基准电路区域（1）和高电位基准电路区域（2）彼此分离。 此外，沟槽（4）填充有绝缘材料，并使低电位参考电路区域（1）和高电位参考电路区域（2）绝缘。 高耐压分离区域（3）由沟槽（4）分隔开，在分隔位置设有高耐压NMOS（5）或高耐压PMOS（6）。

公开(公告)号：US09110119B2

公开(公告)日：2015-08-18

申请号：US13851733

申请日：2013-03-27

申请人： Satoru Sasaki ,  Hideki Tojima ,  Johann Kolar ,  Benjamin Wrzecionko ,  Lukas Steinmann ,  Johann Ertl

发明人： Satoru Sasaki ,  Hideki Tojima ,  Johann Kolar ,  Benjamin Wrzecionko ,  Lukas Steinmann ,  Johann Ertl

IPC分类号： G01R33/02 ,  G01R15/18

CPC分类号： G01R33/02 ,  G01R15/183

摘要： An electric current measurement method is provided with: a first controlling process of sweeping a sensing current in a negative magnetization direction in a condition that a core is saturated magnetically in a positive magnetization direction; a second controlling process of sweeping the sensing current in the positive magnetization direction in a condition that the core is saturated magnetically in the negative magnetization direction; a first specifying process of specifying a value of the sensing current if the core is demagnetized in the first controlling process; a second specifying process of specifying a value of the sensing current if the core is demagnetized in the second controlling process; and a calculating process of calculating a value of a target electric current on the basis of the specified current values, the first and second controlling processes being performed repeatedly.

摘要翻译： 电流测量方法具有：在芯在正磁化方向磁饱和的条件下扫描感测电流在负磁化方向上的第一控制过程; 在磁芯在负磁化方向磁饱和的状态下扫掠正磁化方向上的感测电流的第二控制过程; 第一指定处理，如果在第一控制过程中磁芯被去磁，则指定感测电流的值; 如果在第二控制过程中磁芯被消磁，则指定感测电流的值的第二指定处理; 以及基于规定的电流值来计算目标电流的值的计算处理，重复执行第一和第二控制处理。

公开(公告)号：US08604608B2

公开(公告)日：2013-12-10

申请号：US13448915

申请日：2012-04-17

申请人： Jiro Tsuchiya ,  Torahiko Sasaki ,  Makoto Imai ,  Hideki Tojima ,  Tadakazu Harada ,  Tomoaki Mitsunaga

发明人： Jiro Tsuchiya ,  Torahiko Sasaki ,  Makoto Imai ,  Hideki Tojima ,  Tadakazu Harada ,  Tomoaki Mitsunaga

IPC分类号： H01L23/34 ,  H01L23/10 ,  H05K7/20

CPC分类号： H01L23/473 ,  H01L23/4006 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor module is disclosed that includes a semiconductor element, a capacitor configured to be electrically connected to the semiconductor element and a heat sink, wherein the semiconductor and the capacitor are stacked with each other via the heat sink, and wherein the semiconductor element is disposed in a position overlapping with the capacitor as viewed from a stack direction.

摘要翻译： 公开了一种半导体模块，其包括半导体元件，被配置为电连接到半导体元件的电容器和散热器，其中半导体和电容器经由散热器彼此堆叠，并且其中设置半导体元件 在从堆叠方向观察时与电容器重叠的位置。

公开(公告)号：US20070202661A1

公开(公告)日：2007-08-30

申请号：US11705124

申请日：2007-02-12

申请人： Hiromichi Kinpara ,  Kazuhiko Katami ,  Toru Onishi ,  Hideki Tojima

发明人： Hiromichi Kinpara ,  Kazuhiko Katami ,  Toru Onishi ,  Hideki Tojima

IPC分类号： H01L21/76

CPC分类号： H01L21/76283 ,  H01L21/76286

摘要： [Problem to be Solved] An object is to provide an art for preventing an element formative layer (active layer) from peeling off from a buried insulating film (intermediate insulating layer) with regard to production method of a semiconductor substrate having trench construction.[ Solution ] Production method of a semiconductor substrate, constructed by laminating a support substrate 53, a buried insulating film 52 and an element formative layer 51 in this order and having a trench 56 in the element formative layer 51 for separating an element, comprises a process forming one or plural trenches 56 in the element formative layer 51 along an outer perimeter of an element formative area E so as to connect the element formative area E of the element formative layer 51 to an outer peripheral part thereof at a part thereof at least; a process oxidizing a part of the element formative layer 51 connecting the element formative area E to the outer peripheral part thereof; and a process filling up the trenches 56 with an insulator, thereby forming the trenches 56 in the element formative layer 51 so as to make the element formative area E not independent.

摘要翻译： [待解决的问题]本发明的目的是提供一种防止元件形成层（有源层）相对于具有沟槽结构的半导体衬底的制造方法从埋入绝缘膜（中间绝缘层）剥离的技术。 [解决方案]依次层叠支撑基板53，埋入绝缘膜52和元件形成层51构成的半导体基板的制造方法，在元件形成层51中具有用于分离元件的沟槽56，包括： 沿着元件形成区域E的外周边在元件形成层51中形成一个或多个沟槽56，以将元件形成层51的元件形成区域E至少部分地连接到外周部分 ; 将元件形成区域E连接到其外周部分的元件形成层51的一部分的工艺; 以及用绝缘体填充沟槽56的工艺，从而在元件形成层51中形成沟槽56，以使元件形成区域E不是独立的。

公开(公告)号：US20130278252A1

公开(公告)日：2013-10-24

申请号：US13851733

申请日：2013-03-27

申请人： Satoru SASAKI ,  Hideki TOJIMA ,  Johann KOLAR ,  Benjamin WRZECIONKO ,  Lukas STEINMANN ,  Johann ERTL

发明人： Satoru SASAKI ,  Hideki TOJIMA ,  Johann KOLAR ,  Benjamin WRZECIONKO ,  Lukas STEINMANN ,  Johann ERTL

IPC分类号： G01R33/02

CPC分类号： G01R33/02 ,  G01R15/183

摘要： An electric current measurement method is provided with: a first controlling process of sweeping a sensing current in a negative magnetization direction in a condition that a core is saturated magnetically in a positive magnetization direction; a second controlling process of sweeping the sensing current in the positive magnetization direction in a condition that the core is saturated magnetically in the negative magnetization direction; a first specifying process of specifying a value of the sensing current if the core is demagnetized in the first controlling process; a second specifying process of specifying a value of the sensing current if the core is demagnetized in the second controlling process; and a calculating process of calculating a value of a target electric current on the basis of the specified current values, the first and second controlling processes being performed repeatedly.

摘要翻译： 电流测量方法具有：在芯在正磁化方向磁饱和的条件下扫描感测电流在负磁化方向上的第一控制过程; 在磁芯在负磁化方向磁饱和的状态下扫掠正磁化方向上的感测电流的第二控制过程; 第一指定处理，如果在第一控制过程中磁芯被去磁，则指定感测电流的值; 如果在第二控制过程中磁芯被消磁，则指定感测电流的值的第二指定处理; 以及基于规定的电流值来计算目标电流的值的计算处理，重复执行第一和第二控制处理。

公开(公告)号：US07538407B2

公开(公告)日：2009-05-26

申请号：US10576292

申请日：2004-10-08

申请人： Masato Taki ,  Hideki Tojima

发明人： Masato Taki ,  Hideki Tojima

IPC分类号： H01L29/72

CPC分类号： H01L29/7816 ,  H01L27/092 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7824 ,  H01L29/7835

摘要： A semiconductor apparatus (100) comprises a low potential reference circuit region (1) and a high potential reference circuit region (2), and the high potential reference circuit region (2) is surrounded by a high withstand voltage separating region (3). By a trench (4) formed in the outer periphery of the high withstand voltage separating region (3), the low potential reference circuit region (1) and high potential reference circuit region (2) are separated from each other. Further, the trench (4) is filled up with an insulating material, and insulates the low potential reference circuit region (1) and high potential reference circuit region (2). The high withstand voltage separating region (3) is partitioned by the trench (4), high withstand voltage NMOS (5) or high withstand voltage PMOS (6) is provided in the partitioned position.

摘要翻译： 半导体装置（100）包括低电位基准电路区域（1）和高电位基准电路区域（2），高电位基准电路区域（2）由高耐压分离区域（3）包围。 通过形成在高耐压分离区域（3）的外周的沟槽（4），低电位基准电路区域（1）和高电位基准电路区域（2）彼此分离。 此外，沟槽（4）填充有绝缘材料，并使低电位参考电路区域（1）和高电位参考电路区域（2）绝缘。 高耐压分离区域（3）由沟槽（4）分隔开，在分隔位置设有高耐压NMOS（5）或高耐压PMOS（6）。

公开(公告)号：US20070077501A1

公开(公告)日：2007-04-05

申请号：US11496552

申请日：2006-08-01

申请人： Tsuyoshi Nishiwaki ,  Hideki Tojima

发明人： Tsuyoshi Nishiwaki ,  Hideki Tojima

IPC分类号： G03F1/00 ,  A61N5/00 ,  G21G5/00 ,  G03C5/00

CPC分类号： G03F1/20 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/3174 ,  H01J2237/31711

摘要： The present invention presents a stencil mask in which various surface patterns can be formed, and in which deformation is suppressed when charged particles are introduced. A stencil mask of the present invention is provided with a semiconductor stack. A first penetrating hole corresponding to an ion introducing area is formed in a first semiconductor layer of the semiconductor stack, and second penetrating holes are formed in a second semiconductor layer, these second penetrating holes having a width greater than the width of the first penetrating hole. The first penetrating hole and the second penetrating holes communicate and pass through the semiconductor stack. Beam members extending between adjacent second penetrating holes connect portions of the first semiconductor layer separated by the first penetrating hole.

摘要翻译： 本发明提供一种模板掩模，其中可以形成各种表面图案，并且当引入带电粒子时变形被抑制。 本发明的模板掩模具有半导体叠层。 在半导体堆叠的第一半导体层中形成与离子引入区对应的第一穿透孔，在第二半导体层中形成第二贯通孔，该第二贯通孔的宽度大于第一贯通孔的宽度 。 第一穿透孔和第二穿透孔连通并通过半导体堆叠。 在相邻的第二穿透孔之间延伸的梁构件连接由第一穿透孔分隔开的第一半导体层的部分。

公开(公告)号：US20130009168A1

公开(公告)日：2013-01-10

申请号：US13448915

申请日：2012-04-17

申请人： Jiro TSUCHIYA ,  Torahiko SASAKI ,  Makoto IMAI ,  Hideki TOJIMA ,  Tadakazu HARADA ,  Tomoaki MITSUNAGA

发明人： Jiro TSUCHIYA ,  Torahiko SASAKI ,  Makoto IMAI ,  Hideki TOJIMA ,  Tadakazu HARADA ,  Tomoaki MITSUNAGA

IPC分类号： H01L29/24

CPC分类号： H01L23/473 ,  H01L23/4006 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor module is disclosed that includes a semiconductor element, a capacitor configured to be electrically connected to the semiconductor element and a heat sink, wherein the semiconductor and the capacitor are stacked with each other via the heat sink, and wherein the semiconductor element is disposed in a position overlapping with the capacitor as viewed from a stack direction.

摘要翻译： 公开了一种半导体模块，其包括半导体元件，被配置为电连接到半导体元件的电容器和散热器，其中半导体和电容器经由散热器彼此堆叠，并且其中设置半导体元件 在从堆叠方向观察时与电容器重叠的位置。

公开(公告)号：US07824825B2

公开(公告)日：2010-11-02

申请号：US11496552

申请日：2006-08-01

申请人： Tsuyoshi Nishiwaki ,  Hideki Tojima

发明人： Tsuyoshi Nishiwaki ,  Hideki Tojima

IPC分类号： G03F1/00 ,  G03F7/20 ,  G21K5/04

CPC分类号： G03F1/20 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/3174 ,  H01J2237/31711

摘要： The present invention presents a stencil mask in which various surface patterns can be formed, and in which deformation is suppressed when charged particles are introduced. A stencil mask of the present invention is provided with a semiconductor stack. A first penetrating hole corresponding to an ion introducing area is formed in a first semiconductor layer of the semiconductor stack, and second penetrating holes are formed in a second semiconductor layer, these second penetrating holes having a width greater than the width of the first penetrating hole. The first penetrating hole and the second penetrating holes communicate and pass through the semiconductor stack. Beam members extending between adjacent second penetrating holes connect portions of the first semiconductor layer separated by the first penetrating hole.

摘要翻译： 本发明提供一种模板掩模，其中可以形成各种表面图案，并且当引入带电粒子时变形被抑制。 本发明的模板掩模具有半导体叠层。 在半导体堆叠的第一半导体层中形成与离子引入区对应的第一穿透孔，在第二半导体层中形成第二贯通孔，该第二贯通孔的宽度大于第一贯通孔的宽度 。 第一穿透孔和第二穿透孔连通并通过半导体堆叠。 在相邻的第二穿透孔之间延伸的梁构件连接由第一穿透孔分隔开的第一半导体层的部分。