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    Retainer for Gas Processing Device, Gas Processing Device, and Manufacturing Methods Therefor
    2.
    发明申请
    Retainer for Gas Processing Device, Gas Processing Device, and Manufacturing Methods Therefor 有权
    气体处理装置保持器，气体处理装置及其制造方法

    公开(公告)号：US20140248189A1

    公开(公告)日：2014-09-04

    申请号：US14237295

    申请日：2012-07-19

    申请人： Nobuya Tomosue ,  Hiroki Nakamura ,  Tadashi Sakane

    发明人： Nobuya Tomosue ,  Hiroki Nakamura ,  Tadashi Sakane

    IPC分类号： F01N3/28 ,  B01D53/94

    CPC分类号： F01N3/2871 ,  B01D53/94 ,  F01N3/0211 ,  F01N3/2853 ,  F01N13/16 ,  F01N2330/06 ,  F01N2350/02 ,  F01N2450/02 ,  F01N2450/28 ,  Y02T10/20 ,  Y10T29/49345

    摘要： A gas processing device is disclosed that makes it possible to appropriately control the frictional resistance between a holding mat and a casing. A gas processing device (1) includes a processing structure (20), a casing (40) made of a metal and housing the processing structure (20), and a holding mat (10) formed of inorganic fibers and placed between the processing structure (20) and the casing (40), an inner surface (41) of the casing (40) and an outer surface (11) of the holding mat (10) coming in contact with each other through an adhesive layer (12) that includes a compound that includes a structural unit represented by a general formula (I). wherein R1 are independently a hydrogen atom, an alkyl group having 1 to 5 carbon atoms, an alkoxy group having 1 to 5 carbon atoms, a phenyl group, or a hydroxyl group, and n is an integer equal to or larger than 1.

    摘要翻译： 公开了一种能够适当地控制保持垫和壳体之间的摩擦阻力的气体处理装置。 一种气体处理装置（1）包括处理结构（20），由金属制成并容纳处理结构（20）的壳体（40）和由无机纤维形成的保持垫（10），并被放置在处理结构 （20）和壳体（40），壳体（40）的内表面（41）和保持垫（10）的外表面（11）通过粘合剂层（12）彼此接触， 包括具有由通式（I）表示的结构单元的化合物。 其中R1独立地为氢原子，具有1-5个碳原子的烷基，具有1至5个碳原子的烷氧基，苯基或羟基，并且n为等于或大于1的整数。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08772881B2

    公开(公告)日：2014-07-08

    申请号：US12794088

    申请日：2010-06-04

    申请人： Fujio Masuoka ,  Hiroki Nakamura

    发明人： Fujio Masuoka ,  Hiroki Nakamura

    IPC分类号： H01L27/11 ,  H01L27/088

    CPC分类号： H01L27/1104 ,  H01L27/0207 ,  H01L27/11

    摘要： The object to provide a highly-integrated SGT-based SRAM is achieved by forming an SRAM using an inverter which comprises a first island-shaped semiconductor layer, a first gate dielectric film in contact with a periphery of the first island-shaped semiconductor layer, a first gate electrode having one surface in contact with the first gate dielectric film, a second gate dielectric film in contact with another surface of the first gate electrode, a first arc-shaped semiconductor layer in contact with the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer arranged on a top of the first island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer arranged underneath the first island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer arranged on a top of the first arc-shaped semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer arranged underneath the first arc-shaped semiconductor layer.

    摘要翻译： 提供高度集成的基于SGT的SRAM的目的是通过使用逆变器形成SRAM来实现，该逆变器包括第一岛状半导体层，与第一岛状半导体层的周边接触的第一栅极电介质膜， 具有与第一栅极电介质膜接触的一个表面的第一栅极电极，与第一栅电极的另一表面接触的第二栅极电介质膜，与第二栅极电介质膜接触的第一弧形半导体层，第一栅极电极 布置在第一岛状半导体层的顶部上的第一导电型高浓度半导体层，布置在第一岛状半导体层下方的第二第一导电型高浓度半导体层，第一导电型高浓度半导体层，第一导电型高浓度半导体层， 布置在第一弧形半导体层的顶部上的高浓度半导体层和第二第二导电型高浓度半导体层 所述半导体层布置在所述第一弧形半导体层下方。

    Semiconductor device and production method
    4.
    发明授权
    Semiconductor device and production method 有权

    公开(公告)号：US08558317B2

    公开(公告)日：2013-10-15

    申请号：US12854564

    申请日：2010-08-11

    申请人： Fujio Masuoka ,  Hiroki Nakamura

    发明人： Fujio Masuoka ,  Hiroki Nakamura

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823885 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

    摘要： The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises: a first transistor including; an first island-shaped semiconductor layer; a first gate insulating film; a gate electrode; a first first-conductive-type high-concentration semiconductor layer arranged above the first island-shaped semiconductor layer; and a second first-conductive-type high-concentration semiconductor layer arranged below the first island-shaped semiconductor layer, and a second transistor including; a second gate insulating film surrounding a part of the periphery of the gate electrode; a second semiconductor layer in contact with a part of the periphery of the second gate insulating film; a first second-conductive-type high-concentration semiconductor layer arranged above the second semiconductor layer; and a second second-conductive-type high-concentration semiconductor layer arranged below the second semiconductor layer.

    Semiconductor device and method of producing the same
    5.
    发明授权
    Semiconductor device and method of producing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08395208B2

    公开(公告)日：2013-03-12

    申请号：US13478359

    申请日：2012-05-23

    申请人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

    发明人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

    IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119 ,  H01L31/113

    CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66772

    摘要： It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.

    摘要翻译： 本发明的目的是提供一种能够获得用于降低栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及柱状半导体的期望直径的结构的SGT制造方法。 该目的通过一种半导体器件制造方法来实现，该方法包括以下步骤：形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极的顶部接触的侧壁状的电介质膜; 在所述浇口的侧壁上形成侧壁状的电介质膜; 以及在柱状第一导电型半导体层的上部和形成在柱状的第一导电型半导体层下方的第二导电型半导体层上形成第二导电型半导体层。

    Nonvolatile semiconductor memory transistor and method for manufacturing nonvolatile semiconductor memory
    6.
    发明授权
    Nonvolatile semiconductor memory transistor and method for manufacturing nonvolatile semiconductor memory 有权
    非易失性半导体存储晶体管及其制造方法

    公开(公告)号：US08349688B2

    公开(公告)日：2013-01-08

    申请号：US13178315

    申请日：2011-07-07

    申请人： Fujio Masuoka ,  Hiroki Nakamura

    发明人： Fujio Masuoka ,  Hiroki Nakamura

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/7889 ,  H01L21/28273 ,  H01L27/11521

    摘要： A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the Si substrate side, a floating gate surrounding the outer periphery of the channel region with a tunnel insulating film interposed therebetween, a control gate surrounding the outer periphery of the floating gate with an inter-polysilicon insulating film interposed therebetween, and a control gate line connected to the control gate and extending in a predetermined direction. The floating gate extends to regions below and above the control gate and to a region below the control gate line. The inter-polysilicon insulating film is interposed between the floating gate and the upper surface, lower surface, and inner side surface of the control gate and between the control gate line and a portion of the floating gate that extends to the region below the control gate line.

    摘要翻译： 非易失性半导体存储晶体管包括岛状半导体，其具有从Si衬底侧依次形成的源极区，沟道区和漏极区，围绕沟道区的外周的浮栅与隧道绝缘膜 插入其间的控制栅极，其间隔着多晶硅间绝缘膜围绕浮置栅极的外周，以及连接到控制栅极并沿预定方向延伸的控制栅极线。 浮栅延伸到控制栅极下方和上方的区域以及控制栅极线下方的区域。 多晶硅间绝缘膜介于浮动栅极与控制栅极的上表面，下表面和内侧表面之间，以及控制栅极线与延伸到控制栅极下方区域的浮栅的一部分之间 线。

    GAMING MACHINE RUNNING COMPETING GAME BETWEEN GAMING TERMINALS
    8.
    发明申请
    GAMING MACHINE RUNNING COMPETING GAME BETWEEN GAMING TERMINALS 有权
    游戏终端之间的游戏机运行竞赛游戏

    公开(公告)号：US20120252561A1

    公开(公告)日：2012-10-04

    申请号：US13426000

    申请日：2012-03-21

    申请人： Kenta KITAMURA ,  Masumi Fujisawa ,  Hiroki Nakamura

    发明人： Kenta KITAMURA ,  Masumi Fujisawa ,  Hiroki Nakamura

    IPC分类号： A63F9/24

    CPC分类号： G07F17/3279 ,  G07F17/3211 ,  G07F17/3223 ,  G07F17/3267

    摘要： The present invention provides a gaming machine including gaming terminals having high payout rate without increasing loss on the management side. When a result of a base game associated with a payout is obtained, the gaming machine determines whether at least a competing game condition associated with the payout is satisfied or not and, when it is determined that the competing game condition is satisfied, sets neighboring gaming terminals as opponents. When the opponent participates in a competing game, a competing game for winning a payout by competing against the opponent is run. According to a result of the competing game, at least a part of the payout is given to the winner of the competing game, and no payout is given to the loser of the competing game.

    摘要翻译： 本发明提供一种游戏机，其包括具有高支付率的游戏终端，而不增加管理侧的损失。 当获得与付款相关联的基本游戏的结果时，游戏机确定是否满足与支付相关联的至少竞争游戏条件，并且当确定竞争游戏条件被满足时，设置相邻游戏 终端为对手。 当对手参与竞争游戏时，竞争对手通过与对手进行竞争来赢得支付。 根据竞争游戏的结果，至少一部分支付给予竞争游戏的赢家，并且没有给予竞争游戏的输家。

    Semiconductor surrounding gate transistor device and production method therefor
    10.
    发明授权
    Semiconductor surrounding gate transistor device and production method therefor 有权
    半导体周边栅晶体管器件及其制作方法

    公开(公告)号：US08241976B2

    公开(公告)日：2012-08-14

    申请号：US12704000

    申请日：2010-02-11

    申请人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

    发明人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

    IPC分类号： H01L21/8232

    CPC分类号： H01L29/78642 ,  H01L22/26

    摘要： The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer.

    摘要翻译： 该方法包括以下步骤：在形成在基板上的氧化膜上形成平面半导体层，然后在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在柱状的第一导电型半导体层周围形成栅极电介质膜和由金属制成的栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层。