公开(公告)号：US20140104916A1

公开(公告)日：2014-04-17

申请号：US14105280

申请日：2013-12-13

申请人： Hiromasa NODA ,  Yasuji KOSHIKAWA

发明人： Hiromasa NODA ,  Yasuji KOSHIKAWA

IPC分类号： G11C5/02

CPC分类号： G11C5/02 ,  G11C5/025 ,  G11C8/10 ,  G11C11/4097

摘要： A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.

摘要翻译： 半导体器件包括沿X方向布置的多个存储器垫，以及基于行地址激活存储器垫的一部分并且保持其余的存储器衬垫不被激活的衬垫选择电路。 存储器垫被分成多个存储器垫组，每个存储器垫组包括沿X方向布置的相同数量的存储器垫。 垫选择电路激活包括在每个存储器垫组中的至少一个存储器垫，同时保持其余的存储器垫不被激活。 通过这种操作，在X方向上排列的存储垫中不会发生一部分不连续性，因此消除了在不连续部分中布置两个子字驱动器区域的必要性。

公开(公告)号：US08659321B2

公开(公告)日：2014-02-25

申请号：US13306560

申请日：2011-11-29

申请人： Yuko Watanabe ,  Yoshiro Riho ,  Hiromasa Noda ,  Yoji Idei ,  Kosuke Goto

发明人： Yuko Watanabe ,  Yoshiro Riho ,  Hiromasa Noda ,  Yoji Idei ,  Kosuke Goto

IPC分类号： G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076

摘要： A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.

摘要翻译： 半导体器件包括用于向读出放大器的第一电源节点提供第一电位的第一驱动器电路，用于向读出放大器的第二电源节点提供第二电位和第三电位的第二和第三驱动器电路，以及 用于控制第一至第三驱动器电路的操作的定时控制电路。 定时控制电路包括用于决定第三驱动电路的接通时间的延迟电路。 延迟电路包括具有取决于外部电源电位的延迟量的第一延迟电路和具有不依赖于外部电源电位的延迟量的第二延迟电路，并且第三驱动电路的导通周期为 基于第一和第二延迟电路的延迟量的总和来决定。

公开(公告)号：US08274855B2

公开(公告)日：2012-09-25

申请号：US13168804

申请日：2011-06-24

申请人： Tetsuaki Okahiro ,  Hiromasa Noda ,  Katsunobu Noguchi

发明人： Tetsuaki Okahiro ,  Hiromasa Noda ,  Katsunobu Noguchi

IPC分类号： G11C7/00

CPC分类号： G11C11/408 ,  G11C11/406 ,  G11C16/3418 ,  G11C29/783

摘要： A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.

摘要翻译： 根据本发明的半导体器件具有用于执行地址的地址加扰操作的地址加扰电路和用于判断对由地址加扰电路加扰的地址执行冗余判断的冗余判定电路。 该结构使得可以完全刷新与正常字线和冗余字线有关的操作。

公开(公告)号：US20120158347A1

公开(公告)日：2012-06-21

申请号：US13324567

申请日：2011-12-13

申请人： Hiromasa NODA ,  Toshio Ninomiya

发明人： Hiromasa NODA ,  Toshio Ninomiya

IPC分类号： G06F19/00

CPC分类号： G11C29/028 ,  G11C29/021 ,  G11C29/023

摘要： A device includes a decoder, a selector, and a plurality of registers. The decoder is configured to generate a plurality of test signals. The selector is coupled to the decoder. The selector is configured to sequentially select a test signal from the plurality of test signals and to sequentially output the test signal selected. The plurality of registers is coupled in series to each other. The plurality of registers includes a first stage register. The first stage register is coupled to the selector to sequentially receive the test signal from the selector.

摘要翻译： 一种装置包括解码器，选择器和多个寄存器。 解码器被配置为产生多个测试信号。 选择器耦合到解码器。 选择器被配置为从多个测试信号中顺序地选择测试信号，并且顺序地输出所选择的测试信号。 多个寄存器彼此串联耦合。 多个寄存器包括第一级寄存器。 第一级寄存器耦合到选择器以顺序地从选择器接收测试信号。

公开(公告)号：US20120134439A1

公开(公告)日：2012-05-31

申请号：US13286665

申请日：2011-11-01

申请人： Takenori Sato ,  Yoji Idei ,  Hiromasa Noda

发明人： Takenori Sato ,  Yoji Idei ,  Hiromasa Noda

IPC分类号： H04L27/00 ,  H03K19/0175 ,  H03L5/00

CPC分类号： G11C11/4093 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  H03K3/356104

摘要： A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.

摘要翻译： 半导体器件包括：具有基本相同的电路配置的两个电平移位电路; 输入电路，分别向电平移位电路提供互补输入信号; 以及输出电路，其将从电平移位电路输出的互补输出信号转换为同相信号，然后使同相信号短路。 根据本发明，使用具有基本相同电路结构的两电平移位电路，并且从电平移位电路输出的互补输出信号在短路之前被转换为同相信号。 由于电平移位电路之间的操作速度的差异，几乎不会发生任何直流电流的发生。

公开(公告)号：US20120127814A1

公开(公告)日：2012-05-24

申请号：US13302772

申请日：2011-11-22

申请人： Yoshiro RIHO ,  Hiromasa NODA ,  Kazuki SAKUMA

发明人： Yoshiro RIHO ,  Hiromasa NODA ,  Kazuki SAKUMA

IPC分类号： G11C29/00

CPC分类号： G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/12005 ,  G11C29/28 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/2602

摘要： A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed. Therefore, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced

摘要翻译： 半导体器件包括由多个读出放大器阵列分成多个存储单元阵列的存储单元阵列。 多个存储单元垫中的每一个包括多个字线和用于执行测试控制的测试电路，以一次激活多个选定的未设置的存储单元垫中的每一个字线 在多个存储单元垫中彼此相邻。 分配具有多个激活字线的存储单元垫。 因此，施加到用于驱动字线的驱动电路的负载和施加到用于向驱动器电路提供工作电压的电源电路的负载减小

公开(公告)号：US07969765B2

公开(公告)日：2011-06-28

申请号：US12285527

申请日：2008-10-08

申请人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

IPC分类号： G11C11/24

CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

公开(公告)号：US20090268542A1

公开(公告)日：2009-10-29

申请号：US12500023

申请日：2009-07-09

申请人： Hiromasa NODA

发明人： Hiromasa NODA

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C29/02 ,  G11C7/1045 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2227

摘要： A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.

摘要翻译： 半导体存储器件包括行控制电路块和列控制电路块，每个行控制电路块执行存储单元阵列上的访问控制，数据I / O电路块向存储单元阵列发送数据和从存储单元阵列接收数据;以及控制电路 响应于将预定模式信号设置到模式寄存器，将行控制电路块，列控制电路块和数据I / O电路块的至少一部分改变为从待机状态变为有效状态。 根据本发明，即使需要通过除了读取或写入操作之外的操作将预定的电路块转变为活动状态，也不需要总是将这些电路块设置为活动状态。

公开(公告)号：US20090059702A1

公开(公告)日：2009-03-05

申请号：US12285527

申请日：2008-10-08

申请人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

IPC分类号： G11C7/06

CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

公开(公告)号：US07447091B2

公开(公告)日：2008-11-04

申请号：US11706409

申请日：2007-02-15

申请人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。