公开(公告)号：US08717557B2

公开(公告)日：2014-05-06

申请号：US13578581

申请日：2011-02-16

Applicant: Hayato Tobe ,  Yoichi Sato ,  Hiroyasu Ishida ,  Takayuki Wakui

Inventor： Hayato Tobe ,  Yoichi Sato ,  Hiroyasu Ishida ,  Takayuki Wakui

IPC: G01J3/44

CPC classification number: G01J3/10 ,  G01J3/02 ,  G01J3/0297

Abstract: A spectrophotometer includes a xenon flash lamp, a spectroscope, and a light detector, wherein the spectrophotometer is configured to arrange a low-pressure mercury lamp on a bundle of light rays between the xenon flash lamp and the spectroscope on an as needed basis upon a performance determination of the spectrophotometer, and has a shutter mechanism that switches between shielding the bundle of light rays emitted from the low-pressure mercury lamp and allowing the bundle of light rays to pass through. A processing unit determines the performance of the spectrophotometer by detecting each of the light intensities with the light detector at the time when shielding the bundle of light rays and at the time when allowing the bundle of light rays by operating the shutter mechanism.

Abstract translation: 分光光度计包括氙闪光灯，分光镜和光检测器，其中分光光度计被配置为在氙闪光灯和分光器之间根据需要将低压汞灯布置在一束光线上 分光光度计的性能测定，并且具有遮挡从低压汞灯发射的光线束并允许光束通过的快门机构。 处理单元通过在屏蔽该束光束时和在通过操作快门机构允许光束束时检测光检测器中的每一个光强来确定分光光度计的性能。

公开(公告)号：US20120307240A1

公开(公告)日：2012-12-06

申请号：US13578581

申请日：2011-02-16

Applicant: Hayato Tobe ,  Yoichi Sato ,  Hiroyasu Ishida ,  Takayuki Wakui

Inventor： Hayato Tobe ,  Yoichi Sato ,  Hiroyasu Ishida ,  Takayuki Wakui

IPC: G01J3/10

CPC classification number: G01J3/10 ,  G01J3/02 ,  G01J3/0297

Abstract: Provided are a spectrophotometer using a xenon flash lamp and which can compare with data stored in the past, and a method for determining the performance of the spectrophotometer. In normal times, spectroscopic analysis is performed by employing a bundle of light rays emitted from the xenon flash lamp, spectrally separating the bundle of light rays into arbitrarily-defined wavelengths with a spectroscope through a concave mirror, and detecting the bundle of light rays having passed through a sample with a photodetector. When the performance is to be determined, a low-pressure mercury lamp is arranged in a path of the bundle of light rays between the xenon flash lamp and the spectroscope, a light-shield plate which constitutes a shutter mechanism is operated to shield the light and allow the light to pass through, and the intensity of the light is detected, to thereby determine the “wavelength accuracy” or the “resolution” by employing the bright-line spectrum of the low-pressure mercury lamp. Thus, spectroscopic analysis can be performed while allowing to compare with data stored in the past to be made.

Abstract translation: 提供了使用氙闪光灯的分光光度计，其可以与过去存储的数据进行比较，以及用于确定分光光度计的性能的方法。 通常，通过使用从氙闪光灯发射的一束光线进行光谱分析，通过凹面镜将分光镜将光束光谱分离成任意限定的波长，并且检测具有 用光电检测器通过样品。 当确定性能时，在氙闪光灯和分光镜之间的光束束的路径中布置低压汞灯，操作构成快门机构的遮光板来屏蔽光 并且允许光通过，并且检测光的强度，从而通过采用低压汞灯的亮线谱确定波长精度或分辨率。 因此，可以进行光谱分析，同时允许与要制作的过去存储的数据进行比较。

公开(公告)号：US08253207B2

公开(公告)日：2012-08-28

申请号：US12645942

申请日：2009-12-23

Applicant: Shuji Yoneda ,  Hiroyasu Ishida ,  Makoto Oikawa

Inventor： Shuji Yoneda ,  Hiroyasu Ishida ,  Makoto Oikawa

IPC: H01L27/11

CPC classification number: H01L27/0652 ,  H01L29/0696 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/866 ,  H03K17/163

Abstract: By integrating a diode and a resistor connected in parallel into the same chip as an IGBT and connecting a cathode of the diode to a gate of the IGBT, the value of dv/dt can be limited to a predetermined range inside the chip of the IGBT without a deterioration in turn-on characteristics. Since the chip includes a resistor having such a resistance that a dv/dt breakdown of the IGBT can be prevented, the IGBT can be prevented from being broken by an increase in dv/dt at a site (user site) to which the chip is supplied.

Abstract translation: 通过将二极管和电阻并联连接到与IGBT相同的芯片上并将二极管的阴极连接到IGBT的栅极，dv / dt的值可以限制在IGBT的芯片内部的预定范围内 没有导通特性的恶化。 由于芯片包括具有能够防止IGBT的dv / dt击穿的电阻的电阻器，因此可以防止IGBT在芯片的场所（用户现场）处的dv / dt增加而被破坏 提供。

公开(公告)号：US07528441B2

公开(公告)日：2009-05-05

申请号：US11839293

申请日：2007-08-15

Applicant: Hiroyasu Ishida ,  Tadashi Natsume

Inventor： Hiroyasu Ishida ,  Tadashi Natsume

IPC: H01L27/108

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/7811

Abstract: Provided is an insulated gate semiconductor device. In the device, source regions are provided in the entire operation area and a first back gate region is provided below the source region between trenches. Moreover, a second back gate region connected to the first back gate region is provided outside of the source regions. Thereafter, a first electrode layer coming into contact with the source regions is provided in the entire operation area, and a second electrode layer coming into contact with the second back gate regions is provided around the first electrode layer. Accordingly, potentials can be individually applied to the first electrode layer and the second electrode layer. Thus, it is possible to perform control for preventing reverse flow caused by a parasitic diode.

Abstract translation: 提供绝缘栅半导体器件。 在器件中，源区域设置在整个操作区域中，并且在沟槽之间的源极区域的下方提供第一后栅极区域。 此外，连接到第一背栅极区域的第二背栅极区域设置在源极区域的外部。 此后，在整个操作区域中设置与源极区域接触的第一电极层，并且在第一电极层周围设置与第二背栅极区域接触的第二电极层。 因此，电位可以单独施加到第一电极层和第二电极层。 因此，可以执行用于防止由寄生二极管引起的反向流动的控制。

公开(公告)号：US20080079079A1

公开(公告)日：2008-04-03

申请号：US11860689

申请日：2007-09-25

Applicant: Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

Inventor： Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

IPC: H01L27/06

CPC classification number: H01L29/7811 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/4238 ,  H01L29/7808 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.

Abstract translation: 与晶体管单元连续的沟道区也设置在栅极焊盘电极下方。 栅极焊盘电极下方的沟道区域固定为源极电位。 因此，确保漏极和源极之间的预定的反向击穿电压，而不在栅极焊盘电极的整个下表面下方形成p +型杂质区域。 此外，保护二极管形成在栅极电极下方具有条纹形状的多晶硅中。

公开(公告)号：US20070262390A1

公开(公告)日：2007-11-15

申请号：US11797900

申请日：2007-05-08

Applicant: Hiroyasu Ishida ,  Yasunari Noguchi

Inventor： Hiroyasu Ishida ,  Yasunari Noguchi

IPC: H01L29/94

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: Channel regions and gate electrodes are also disposed continuously with transistor cells below a gate pad electrode. The transistor cells are formed in a stripe pattern and allowed to contact a source electrode. In this way, the channel regions and the gate electrodes, which are positioned below the gate pad electrode, are kept at a predetermined potential. Thus, a predetermined drain-source reverse breakdown voltage can be secured without providing a p+ type impurity region on the entire surface below the gate pad electrode.

Abstract translation: 通道区域和栅电极也与栅极焊盘电极下面的晶体管单元连续地设置。 晶体管单元形成为条状图案并允许与源极接触。 以这种方式，位于栅极焊盘电极下方的沟道区域和栅极电极保持在预定电位。 因此，可以确保在栅极焊盘电极下方的整个表面上不提供p + +型杂质区域的预定漏极 - 源极反向击穿电压。

公开(公告)号：US20060220122A1

公开(公告)日：2006-10-05

申请号：US11373488

申请日：2006-03-13

Applicant: Yasuyuki Sayama ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Kazunari Kushiyama

Inventor： Yasuyuki Sayama ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Kazunari Kushiyama

IPC: H01L29/76

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712

Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.

Abstract translation: 在栅电极的下方设置有n型杂质区。 通过将栅极长度设置为小于沟道区的深度，沟道区的侧表面和与沟道区相邻的n型杂质区的侧表面形成基本上垂直的接合表面。 因此，由于耗尽层在衬底的深度方向上均匀地变宽，因此可以确保预定的击穿电压。 此外，由于栅极电极上方的沟道区域之间的间隔从表面到底部均匀，所以可以增加n型杂质区域的杂质浓度，导致实现低的导通 -抵抗性。

公开(公告)号：US20050255706A1

公开(公告)日：2005-11-17

申请号：US11123248

申请日：2005-05-06

Applicant: Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

Inventor： Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

IPC: H01L21/28 ,  H01L21/30 ,  H01L21/31 ,  H01L21/322 ,  H01L21/336 ,  H01L21/469 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/74 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L21/3003 ,  H01L21/76886 ,  H01L21/823487 ,  H01L29/456

Abstract: In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.

Abstract translation: 在MOSFET中，在形成元件区之后，在阻挡金属层的后面形成布线层，进行氢退火。 然而，在n沟道MOSFET的情况下，由于阻挡金属层的遮挡特性，阈值电压降低。 因此，通道层中杂质浓度的增加引起导通电阻的降低被抑制的问题。 根据本发明，在形成阻挡金属层之后，在层间绝缘膜上的阻挡金属层中设置开口，在形成布线层之后进行氢退火处理。 因此，到达基板的氢的量进一步增加，并且抑制了阈值电压的降低。 此外，由于可以降低沟道层中的杂质浓度，所以导通电阻降低。

公开(公告)号：US5001198A

公开(公告)日：1991-03-19

申请号：US306987

申请日：1989-02-06

Applicant: Akira Sekiya ,  Masanori Tamura ,  Hiroyasu Ishida

Inventor： Akira Sekiya ,  Masanori Tamura ,  Hiroyasu Ishida

IPC: C08F8/18 ,  C08F8/20

CPC classification number: C08F8/18

Abstract: A novel fluorine-containing polymeric compound represented by the general formula--CH.sub.2 --CH[(CH.sub.2).sub.a --NH.sub.2 ]}.sub.m-n--CH.sub.2 --CH[(CH.sub.2).sub.a --NH--CO--NH--CH.sub.2).sub.a Rf]}.sub.n,in which Rf is a perfluoroalkyl group having 6 to 15 carbon atoms, m is a positive integer in the range from 10 to 1500, n is a positive integer smaller than 0.7 m and a is 0 or 1, is prepared by the reaction of, when a is 0, a polyvinylamine of the formula --CH.sub.2 --CHNH.sub.2 ].sub.m, with an alkyl perfluoroalkanoate of the formula Rf--CO--OR, in which R is an alkyl group having 1 to 5 carbon atoms, or, when a is 1, a polyallylamine of the formula --CH.sub.2 --CH(CH.sub.2 --NH.sub.2)].sub.m, with a perfluoroalkylmethyl isocyanate of the formula RfCH.sub.2 --NCO. Despite the high fluorine content, the polymer is soluble in at least one kind of organic solvents so that Langmuir-Blodgett's films can be prepared from a solution of the polymer. The LB films have an extremely low surface energy and useful as a material for protection and modification of various surfaces.

公开(公告)号：US07902053B2

公开(公告)日：2011-03-08

申请号：US12199547

申请日：2008-08-27

Applicant: Hiroyasu Ishida ,  Yasuyuki Sayama

Inventor： Hiroyasu Ishida ,  Yasuyuki Sayama

IPC: H01L21/20

CPC classification number: H01L29/0634 ,  H01L21/26586

Abstract: Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.

Abstract translation: n型外延层的形成和蚀刻以及p型外延层的形成和蚀刻在半导体衬底上交替进行至少三次以形成外延层的所有半导体层。 因此，半导体层的杂质浓度分布可以是均匀的，并且pn结可以垂直于晶片表面形成。 此外，半导体层各自可以形成为窄的宽度，使得其杂质浓度增加。 利用这种结构，可以实现高击穿电压和低电阻。